Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

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Date 12/16/2022
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Document Table of Contents
Document Table of Contents x
FPGA Optimization Guide for Intel® oneAPI Toolkits
FPGA Optimization Guide for Intel® oneAPI Toolkits x
Introduction To FPGA Design Concepts Analyze Your Design Optimize Your Design FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits Notices and Disclaimers
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design Methods of Hardware Design How Source Code Becomes a Custom Hardware Datapath Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
FPGA Architecture Overview x
Adaptive Logic Module (ALM) Lookup Table (LUT) Register Digital Signal Processing (DSP) Block Random Access Memory (RAM) Blocks
Concepts of FPGA Hardware Design x
Maximum Frequency (fMAX) Latency Pipelining Throughput Datapath Control Path Occupancy
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Mapping Arrays and Their Accesses to Hardware
Scheduling x
Dynamic Scheduling Clustering the Datapath Handshaking Between Clusters
Mapping Parallelism Models to FPGA Hardware x
Data Parallelism Task Parallelism
Data Parallelism x
Executing Independent Operations Simultaneously Pipelining
Memory Types x
Kernel Memory Global Memory
Analyze Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image
Analyze the FPGA Early Image x
Review the FPGA Optimization Report Access HLD FPGA Reports in JSON Format
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer
Analyze the FPGA Image x
Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL* Applications
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (<span class='codeph'>-Xsprofile</span>) Obtain Profiling Data During Runtime Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Runtime x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL* Applications x
Set Up the Intercept Layer for OpenCL* Applications
Optimize Your Design x
Throughput Resource Use
Throughput x
Single Work-item Kernels NDRange Kernels Memory Accesses Pipes Host
Single Work-item Kernels x
Single Work-item Kernel Design Guidelines Loops Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Shannonization to Improve FMAX/II Optimize Inner Loop Throughput Improve Loop Performance by Caching On-Chip Memory
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Host x
Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL* Applications
Resource Use x
Data Types and Operations Kernel Variable Accesses
Data Types and Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Integer and Floating-Point Support
Variable-Precision Integer and Floating-Point Support x
Advantages and Limitations of Arbitrary Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the <span class='codeph'>ac_int</span> Data Type Declare the <span class='codeph'>ac_fixed</span> Data Type Declare the <span class='codeph'>ac_complex</span> Data Type Declare the <span class='codeph'>ap_float</span> Data Type
Declare the <span class='codeph'>ap_float</span> Data Type x
Conversion Rules for <span class='codeph'>ap_float</span> Operations with Explicit Precision Controls Comparison Operators Additional <span class='codeph'>ap_float</span> Functions Additional Data Types Provided by the <span class='codeph'>ap_float.hpp</span> Header File Quality of Results and the ap_float Data Type
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Kernel Attributes Kernel Controls Kernel Variables Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta) Use Model Latency Controls and Stall-free Loops Rules and Limitations System of Tasks Extension (<span class='codeph'>task_sequence</span>)
Optimization Flags x
Specify Schedule FMAX Target for Kernels (<span class='codeph'>-Xsclock=<clock target>) Disable Burst-Interleaving of Global Memory (<span class='codeph'>-Xsno-interleaving=<global_memory_type></span>) Force Ring Interconnect for Global Memory (<span class='codeph'>-Xsglobal-ring</span>) Force a Single Store Ring to Reduce Area (<span class='codeph'>-Xsforce-single-store-ring</span>) Force Fewer Read Data Reorder Units to Reduce Area (<span class='codeph'>-Xsnum-reorder</span>) Disable Hardware Kernel Invocation Queue (<span class='codeph'>-Xsno-hardware-kernel-invocation-queue</span>) Modify the Handshaking Protocol Between Clusters (<span class='codeph'>-Xshyper-optimized-handshaking</span>) Disable Automatic Fusion of Loops (<span class='codeph'>-Xsdisable-auto-loop-fusion</span>) Fuse Adjacent Loops With Unequal Trip Counts (<span class='codeph'>-Xsenable-unequal-tc-fusion</span>) Pipeline Loops in Non-task Kernels (<span class='codeph'>-Xsauto-pipeline</span>) Control Semantics of Floating-Point Operations (<span class='codeph'>-fp-model=<var><value></var> </span>) Modify the Rounding Mode of Floating-point Operations (<span class='codeph'>-Xsrounding=<rounding_type></span>) Global Control of Exit FIFO Latency of Stall-free Clusters (<span class='codeph'>-Xssfc-exit-fifo-type=<var><value></var> </span>) Enable the Read-Only Cache for Read-Only Accessors (<span class='codeph'>-Xsread-only-cache-size=<var><N></var>)</span> Control Hardware Implementation of the Supported Data Types and Math Operations (<span class='codeph'>-Xsdsp-mode=<var><option></var> </span>)
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD WorkItems Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the <span class='codeph'>no_global_work_offset</span> Attribute in <span class='codeph'>parallel_for</span> Kernels Reduce Kernel Area and Latency
Kernel Controls x
Pipes Extension
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The <span class='codeph'>pipe</span> Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes Pipe and Atomic Fence
Loop Directives x
<span class='codeph'>disable_loop_pipelining</span> Attribute <span class='codeph'>initiation_interval</span> Attribute <span class='codeph'>ivdep</span> Attribute <span class='codeph'>loop_coalesce</span> Attribute <span class='codeph'>max_concurrency</span> Attribute <span class='codeph'>max_interleaving</span> Attribute <span class='codeph'>speculated_iterations</span> Attribute <span class='codeph'>unroll</span> Pragma Loop Fuse Functions and <span class='codeph'>nofusion</span> Attribute
System of Tasks Extension (<span class='codeph'>task_sequence</span>) x
Task Functions <span class='codeph'>task_sequence</span> Use Cases
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API <span class='codeph'>task_sequence</span> Template Parameters and Function APIs
FPGA Optimization Guide for Intel® oneAPI Toolkits

Latency Controls (Beta)

The Intel® oneAPI DPC++/C++ Compiler allows you to set latency constraints between operations with side effects, such as pipes and LSUs, which are visible outside the kernel. Specifically, you can apply latency controls to pipe read/write and LSU load/store.

For stallable operations, the scheduler considers only the inherent latency of the operation without making any assumption about the actual stall time. The compiler strives to achieve the latency constraints. If it cannot achieve the latency controls, the compiler errors out.

Use Model

CAUTION:

The APIs described in this section are experimental. Future versions of latency controls might change these APIs in ways that are incompatible with the version described here.

Latency control APIs are provided on read() and write() member functions of the sycl::ext::intel::experimental::pipe class, and on load() and store() member functions of the sycl::ext::intel::experimental::lsu class. Other than the latency controls support, the experimental pipe and LSU are identical to sycl::ext::intel::pipe and sycl::ext::intel::lsu, and the <sycl/ext/intel/fpga_extensions.hpp> header file provides experimental pipe and LSU. These member functions (read(), write(), load(), and store()) can accept a property list instance (sycl::ext::oneapi::experimental::properties) as a function argument, which can contain the following latency-control properties:

  • sycl::ext::intel::experimental::latency_anchor_id<N>, where N is a signed integer:

    A label that you can associate with pipes and LSU functions listed above. You can then reference this label using the latency_constraint property to define relative latency constraints. You can refer functions with this property as labeled functions.

  • sycl::ext::intel::experimental::latency_constraint<A, B, C>:

    A constraint that you can associate with pipes and LSU functions listed above. It provides a latency constraint between the function associated with the constraint and a different labeled function. You can refer functions with this property as constrained functions. The latency_constraint property has the following parameters:

    • A (signed integer): The label of the labeled function that is constrained relative to the constrained function.
    • B (enum value): The constraint type that can be one of the following:
      • latency_control_type::exact (exact latency)
      • latency_control_type::max (maximum latency)
      • latency_control_type::min (minimum latency)
    • C (signed integer): The relative clock cycle difference between the labeled function and constrained function that the constraint must infer, subject to the type of constraint (exact, max, or main).

Latency Controls and Stall-free Loops

In general, latency anchors and constraints may not span a loop because the number of cycles the loop takes to execute cannot be determined at compile time. Hence, it is not possible to satisfy the latency constraint.

An exception to this rule is a stall-free loop, which has a compile-time constant integer number of iterations and does not contain any stallable statements. These may include arithmetic operations and loads/stores to local stall-free memory. Stall-free loops execute in a compile-time known number of cycles.

Example of a stall-free loop: 

float Value = <anything>;
float Result = 0;
for (int i = 0; i < 5; i++)  // compile time integer number of iterations
  Result *= (i+Value);       // arithmetic calculation that cannot stall
// Use Result

Example 1: Using Latency Controls on Pipes

The following example shows how to use latency controls on pipes. The example uses a function behaving both as a labeled function and a constrained function: 

using Pipe1 = sycl::ext::intel::experimental::pipe<class PipeClass1, int, 8>;
using Pipe2 = sycl::ext::intel::experimental::pipe<class PipeClass2, int, 8>;
using Pipe3 = sycl::ext::intel::experimental::pipe<class PipeClass2, int, 8>;
...
// In kernel:
// The following read has a label 0.
int value = Pipe1::read(sycl::ext::oneapi::experimental::properties(
  sycl::ext::intel::experimental::latency_anchor_id<0>));

// The following write occurs exactly 2 cycles after the label-0 function, i.e.,
// the read above. Also, it has a label 1.
Pipe2::write(
  value,
  sycl::ext::oneapi::experimental::properties(
    sycl::ext::intel::experimental::latency_anchor_id<1>,
    sycl::ext::intel::experimental::latency_constraint<
      0, sycl::ext::intel::experimental::latency_control_type::exact,
      2>));

// The following write occurs at least 2 cycles after the label-1 function,
// i.e., the write above.
Pipe3::write(
  value,
  sycl::ext::oneapi::experimental::properties(
    sycl::ext::intel::experimental::latency_constraint<
      1, sycl::ext::intel::experimental::latency_control_type::min, 2>));

Example 2: Using Latency Controls on LSUs

The following example shows how to use latency controls on LSUs. It uses a negative relative cycle number in the latency_constraint property, which means that the constrained function is scheduled before the associated labeled function: 

using BurstCoalescedLSU = sycl::ext::intel::experimental::lsu<
  sycl::ext::intel::experimental::burst_coalesce<false>,
  sycl::ext::intel::experimental::statically_coalesce<false>>;
...
// In kernel:
// The following load occurs at most 5 cycles before the label-2 function,
// i.e., the store below.
int value = BurstCoalescedLSU::load(
  input_ptr,
  sycl::ext::oneapi::experimental::properties(
    sycl::ext::intel::experimental::latency_constraint<
      2, sycl::ext::intel::experimental::latency_control_type::max, -5>));

// The following store has a label 2.
BurstCoalescedLSU::store(
  output_ptr, value,
  sycl::ext::oneapi::experimental::properties(
    sycl::ext::intel::experimental::latency_anchor_id<2>));

Using Latency Controls on LSUs With a Stall-free Loop

The following example shows how to use latency controls on LSUs with a stall-free loop. It uses a negative relative cycle number in the latency_constraint property, which means that the constrained function is scheduled before the associated labeled function: 

using BurstCoalescedLSU = sycl::ext::intel::experimental::lsu<
  sycl::ext::intel::experimental::burst_coalesce<false>,
  sycl::ext::intel::experimental::statically_coalesce<false>>;
...
// In kernel:
// The following load occurs at most 25 cycles before the label-2 function,
// i.e., the store below.
int value = BurstCoalescedLSU::load(
  input_ptr,
  sycl::ext::oneapi::experimental::properties(
    sycl::ext::intel::experimental::latency_constraint<
      2, sycl::ext::intel::experimental::latency_control_type::max, -25>));
 
 float Result = 0;
 for (int i = 0; i < 5; i++)
   Result *= (Result-Value);    
// The following store has a label 2.
BurstCoalescedLSU::store(
  output_ptr, Result,
  sycl::ext::oneapi::experimental::properties(
    sycl::ext::intel::experimental::latency_anchor_id<2>));

Rules and Limitations

  • latency_anchor_id must be a non-negative number.
  • latency_anchor_id must be a unique number within the whole design.
  • The labeled function and constrained function of a constraint must meet one of the following conditions:
    • Both functions are in the same block but not in any cluster
    • Both functions are in the same cluster.

The compiler attempts to achieve latency constraints. However, it errors out if some constraints cannot be satisfied. For example, if one constraint specifies function A must be scheduled after function B, while another constraint specifies function B must be scheduled after function A, then that set of constraints is unsatisfiable.

TIP:

For additional information, refer to the FPGA tutorial sample "experimental/Latency Control" listed in the Intel® oneAPI Samples Browser on Linux* or Windows*, or access the code sample on GitHub.

Parent topic: FPGA Optimization Flags, Attributes, Pragmas, and Extensions
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