Developer Guide

FPGA Optimization Guide for Intel® oneAPI Toolkits

Download PDF
ID 767853
Date 12/16/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
FPGA Optimization Guide for Intel® oneAPI Toolkits
FPGA Optimization Guide for Intel® oneAPI Toolkits x
Introduction To FPGA Design Concepts Analyze Your Design Optimize Your Design FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the FPGA Optimization Guide for Intel® oneAPI Toolkits Notices and Disclaimers
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design Methods of Hardware Design How Source Code Becomes a Custom Hardware Datapath Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
FPGA Architecture Overview x
Adaptive Logic Module (ALM) Lookup Table (LUT) Register Digital Signal Processing (DSP) Block Random Access Memory (RAM) Blocks
Concepts of FPGA Hardware Design x
Maximum Frequency (fMAX) Latency Pipelining Throughput Datapath Control Path Occupancy
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Mapping Arrays and Their Accesses to Hardware
Scheduling x
Dynamic Scheduling Clustering the Datapath Handshaking Between Clusters
Mapping Parallelism Models to FPGA Hardware x
Data Parallelism Task Parallelism
Data Parallelism x
Executing Independent Operations Simultaneously Pipelining
Memory Types x
Kernel Memory Global Memory
Analyze Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image
Analyze the FPGA Early Image x
Review the FPGA Optimization Report Access HLD FPGA Reports in JSON Format
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates Messages in the Area Estimates Report System Viewer Kernel Memory Viewer Schedule Viewer
Analyze the FPGA Image x
Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL* Applications
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (<span class='codeph'>-Xsprofile</span>) Obtain Profiling Data During Runtime Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Runtime x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL* Applications x
Set Up the Intercept Layer for OpenCL* Applications
Optimize Your Design x
Throughput Resource Use
Throughput x
Single Work-item Kernels NDRange Kernels Memory Accesses Pipes Host
Single Work-item Kernels x
Single Work-item Kernel Design Guidelines Loops Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Shannonization to Improve FMAX/II Optimize Inner Loop Throughput Improve Loop Performance by Caching On-Chip Memory
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Host x
Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL* Applications
Resource Use x
Data Types and Operations Kernel Variable Accesses
Data Types and Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Integer and Floating-Point Support
Variable-Precision Integer and Floating-Point Support x
Advantages and Limitations of Arbitrary Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the <span class='codeph'>ac_int</span> Data Type Declare the <span class='codeph'>ac_fixed</span> Data Type Declare the <span class='codeph'>ac_complex</span> Data Type Declare the <span class='codeph'>ap_float</span> Data Type
Declare the <span class='codeph'>ap_float</span> Data Type x
Conversion Rules for <span class='codeph'>ap_float</span> Operations with Explicit Precision Controls Comparison Operators Additional <span class='codeph'>ap_float</span> Functions Additional Data Types Provided by the <span class='codeph'>ap_float.hpp</span> Header File Quality of Results and the ap_float Data Type
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Kernel Attributes Kernel Controls Kernel Variables Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta) System of Tasks Extension (<span class='codeph'>task_sequence</span>)
Optimization Flags x
Specify Schedule FMAX Target for Kernels (<span class='codeph'>-Xsclock=<clock target>) Disable Burst-Interleaving of Global Memory (<span class='codeph'>-Xsno-interleaving=<global_memory_type></span>) Force Ring Interconnect for Global Memory (<span class='codeph'>-Xsglobal-ring</span>) Force a Single Store Ring to Reduce Area (<span class='codeph'>-Xsforce-single-store-ring</span>) Force Fewer Read Data Reorder Units to Reduce Area (<span class='codeph'>-Xsnum-reorder</span>) Disable Hardware Kernel Invocation Queue (<span class='codeph'>-Xsno-hardware-kernel-invocation-queue</span>) Modify the Handshaking Protocol Between Clusters (<span class='codeph'>-Xshyper-optimized-handshaking</span>) Disable Automatic Fusion of Loops (<span class='codeph'>-Xsdisable-auto-loop-fusion</span>) Fuse Adjacent Loops With Unequal Trip Counts (<span class='codeph'>-Xsenable-unequal-tc-fusion</span>) Pipeline Loops in Non-task Kernels (<span class='codeph'>-Xsauto-pipeline</span>) Control Semantics of Floating-Point Operations (<span class='codeph'>-fp-model=<var><value></var> </span>) Modify the Rounding Mode of Floating-point Operations (<span class='codeph'>-Xsrounding=<rounding_type></span>) Global Control of Exit FIFO Latency of Stall-free Clusters (<span class='codeph'>-Xssfc-exit-fifo-type=<var><value></var> </span>) Enable the Read-Only Cache for Read-Only Accessors (<span class='codeph'>-Xsread-only-cache-size=<var><N></var>)</span> Control Hardware Implementation of the Supported Data Types and Math Operations (<span class='codeph'>-Xsdsp-mode=<var><option></var> </span>)
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD WorkItems Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the <span class='codeph'>no_global_work_offset</span> Attribute in <span class='codeph'>parallel_for</span> Kernels Reduce Kernel Area and Latency
Kernel Controls x
Pipes Extension
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The <span class='codeph'>pipe</span> Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes Pipe and Atomic Fence
Loop Directives x
<span class='codeph'>disable_loop_pipelining</span> Attribute <span class='codeph'>initiation_interval</span> Attribute <span class='codeph'>ivdep</span> Attribute <span class='codeph'>loop_coalesce</span> Attribute <span class='codeph'>max_concurrency</span> Attribute <span class='codeph'>max_interleaving</span> Attribute <span class='codeph'>speculated_iterations</span> Attribute <span class='codeph'>unroll</span> Pragma Loop Fuse Functions and <span class='codeph'>nofusion</span> Attribute
System of Tasks Extension (<span class='codeph'>task_sequence</span>) x
Task Functions <span class='codeph'>task_sequence</span> Use Cases
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API <span class='codeph'>task_sequence</span> Template Parameters and Function APIs
FPGA Optimization Guide for Intel® oneAPI Toolkits

Area Estimates

The <project_dir>/reports/report.html file contains information about area use of your DPC++ system.

The report provides the following information:

  • Detailed area breakdown of the whole DPC++ system, mapped to your source code where possible.
  • Architectural details to give insight into the generated hardware and offers actionable suggestions to resolve potential inefficiencies.

To view the Area Estimates report, click Area Estimates.

As you can observe in the following figure, the report is divided into three levels of hierarchy:

  • System area: Used by all kernels, pipes, interconnects, and board logic.
  • Kernel area: Used by a specific kernel, including overheads, for example, dispatch logic.
  • Block area: Used by a specific block within a kernel. A block represents a branch-free section of your source code (for example, a loop body). To view the area, use information from the source code lines associated with a block and expand the report entry for that block.
Area Estimates Report Hierarchy

NOTE:

The area use data are estimates that the Intel® oneAPI DPC++/C++ Compiler generates. These estimates might differ from the final area utilization results.

Messages in the Area Estimates Report

After you compile your DPC++ application, review the Area Estimates report that the Intel® oneAPI DPC++/C++ Compiler generates. In addition to summarizing the application’s resource use, the Area Estimates report offers suggestions on modifying your design to improve efficiency. Refer to the following sections that describe various messages reported in the Area Estimates report.

Message for Board Interface

The Area Estimates report identifies the amount of logic that the Intel® oneAPI DPC++/C++ Compiler generates for the Custom Platform or board interface. The board interface is the static region of the device that facilitates communication with external interfaces such as PCIe®. The Custom Platform specifies the size of the board interface.

Message for Function Overhead

The Area Estimates report identifies the amount of logic that the Intel® oneAPI DPC++/C++ Compiler generates for dispatching kernels.

Message for State

The Area Estimates report identifies the number of resources your design uses for live values and control logic. To reduce the reported area consumption under State, modify your design as follows:

  • Decrease the size of local variables.
  • Decrease the scope of local variables by localizing them whenever possible.
  • Decrease the number of nested loops in the kernel.

Message for Feedback

The Area Estimates report specifies the resources that your design uses for loop-carried dependencies.

To reduce the reported area consumption under Feedback, decrease the number and size of loop-carried variables in your design.

Messages for Private Variable Storage

The Area Estimates report provides information on the implementation of private memory based on your DPC++ design. For single work-item kernels, the Intel® oneAPI DPC++/C++ Compiler implements private memory differently, depending on the types of variable. The Intel® oneAPI DPC++/C++ Compiler implements scalars and small arrays in registers of various configurations (for example, plain registers, shift registers, and barrel shifter). The Intel® oneAPI DPC++/C++ Compiler implements larger arrays in block RAM.

The following table lists messages and notes of different private variable storage types:

Additional Information About Area Estimates Report Message

Message

Notes

Implementation of Private Memory Using On-Chip Block RAM

Private memory implemented in on-chip block RAM.

The block RAM implementation creates a system that is similar to local memory for NDRange kernels.

Implementation of Private Memory Using On-Chip Block ROM

—

For each use of an on-chip block ROM, the Intel® oneAPI DPC++/C++ Compiler creates another instance of the same ROM. There is no explicit annotation for private variables that the Intel® oneAPI DPC++/C++ Compiler implements in on-chip block ROM.

Implementation of Private Memory Using Registers

Implemented using registers of the following size:

  • <X> registers of width <Y> bits and depth <Z>.
    • Depth was increased by a factor of <N> due to a loop initiation interval of <M>.
    • Each register is implemented in a RAM-based FIFO and consumes <U> RAMs.
  • ...

Reports that the Intel® oneAPI DPC++/C++ Compiler implements a private variable in registers. The Intel® oneAPI DPC++/C++ Compiler might implement a private variable in many registers. This message provides a list of the registers with their specific widths and depths.

Implementation of Private Memory Using Shift Registers

Implemented as a shift register with <N> or fewer tap points. This is a very efficient storage type.

Implemented using registers of the following sizes:

  • <X> register(s) of width <Y> bits and depth <Z>.
    • Depth was increased by a factor of <N> due to a loop initiation interval of <M>.
    • Each register is implemented in a RAM-based FIFO and consumes <U> RAMs.
  • ...

Reports that the Intel® oneAPI DPC++/C++ Compiler implements a private variable in shift registers. This message provides a list of shift registers with their specific widths and depths.

The Intel® oneAPI DPC++/C++ Compiler might break a single array into several smaller shift registers depending on its tap points.

NOTE:

The compiler might overestimate the number of tap points.

Implementation of Private Memory Using Barrel Shifters with Registers

Implemented as a barrel shifter with registers due to dynamic indexing. This is a high overhead storage type. If possible, change to compile-time known indexing. The area cost of accessing this variable is shown on the lines where the accesses occur.

Implemented using registers of the following size:

  • <X> registers of width <Y> bits and depth <Z>.
    • Depth was increased by a factor of <N> due to a loop initiation interval of <M>.
    • Each register is implemented in a RAM-based FIFO and consumes <U> RAMs.
  • ...

Reports that the Intel® oneAPI DPC++/C++ Compiler implements a private variable in a barrel shifter with registers because of dynamic indexing.

This row in the report does not specify the full area use of the private variable. The report shows additional area use information on the lines where the variable is accessed.

NOTE:
  • The Area Estimates report annotates memory information on the line of code that declares or uses private memory, depending on its implementation.
  • When the Intel® oneAPI DPC++/C++ Compiler implements private memory in on-chip block RAM, the Area Estimates report displays relevant local-memory-specific messages to private memory systems.
Parent topic: Review the FPGA Optimization Report
Level Two Title