Developer Guide and Reference

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ID 767253
Date 10/31/2024
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Document Table of Contents
Document Table of Contents x
Developer Guide and Reference
Developer Guide and Reference x
Intel® oneAPI DPC++/C++ Compiler Introduction Compiler Setup Compiler Reference Compilation Optimization and Programming Compatibility and Portability Notices and Disclaimers
Intel® oneAPI DPC++/C++ Compiler Introduction x
Get Help and Support Related Information
Compiler Setup x
Use the Command Line Use Eclipse Use Microsoft Visual Studio
Use the Command Line x
Specify Component Locations Invoke the Compiler Use the Command Line on Windows File Extensions Use Makefiles for Compilation Use CMake with the Compiler Use Compiler Options Specify Compiler Files Convert Projects to Use a Selected Compiler
Use Eclipse x
Add the Compiler to Eclipse Multiversion Compiler Support Use Cheat Sheets Create a Simple Eclipse Project Makefiles Use Intel Libraries with Eclipse
Use Microsoft Visual Studio x
Create a New Project Use the Intel® oneAPI DPC++/C++ Compiler Select the Compiler Version Specify a Base Platform Toolset Use Property Pages Use Intel® Libraries with Microsoft Visual Studio* Include MPI Support Use Code Coverage in Microsoft Visual Studio* Use Profile Guided Optimization in Microsoft Visual Studio* Optimization Reports in Microsoft Visual Studio* Dialog Box Help
Dialog Box Help x
Use Intel® oneAPI DPC++/C++ Compiler dialog box Hardware Profile-Guided Optimization dialog box Options: Compilers dialog box Options: Intel Libraries for oneAPI dialog box Options: Converter dialog box Options: Optimization Reports dialog box Options: Profile Guided Optimization dialog box Profile Guided Optimization dialog box Options: Code Coverage dialog box Code Coverage dialog box Code Coverage Settings dialog box
Compiler Reference x
C/C++/SYCL Calling Conventions Compiler Options Floating-Point Operations Attributes Intrinsics Libraries Macros Pragmas Syntactic and Semantic Errors
Compiler Options x
Alphabetical Option List General Rules for Compiler Options What Appears in the Compiler Option Descriptions Optimization Options Advanced Optimization Options Code Generation Options Offload Compilation, OpenMP*, and Parallel Processing Options Interprocedural Optimization Options Profile Guided Optimization Options Optimization Report Options Floating-Point Options Inlining Options Output, Debug, and Precompiled Header Options Preprocessor Options Component Control Options Language Options Data Options Compiler Diagnostic Options Compatibility Options Linking or Linker Options Miscellaneous Options Deprecated and Removed Compiler Options Display Option Information Alternate Compiler Options Portability and GCC-Compatible Warning Options
Optimization Options x
fast fbuiltin, Oi foptimize-sibling-calls GF nolib-inline O Od Ofast Os Ot Ox
Advanced Optimization Options x
ffreestanding, Qfreestanding fjump-tables fvec-allow-scalar-stores, Qvec-allow-scalar-stores fvec-peel-loops, Qvec-peel-loops fvec-remainder-loops, Qvec-remainder-loops fvec-with-mask, Qvec-with-mask ipp-link, Qipp-link mno-gather, Qgather- mno-scatter, Qscatter- qactypes, Qactypes qdaal, Qdaal qipp, Qipp qmkl, Qmkl qmkl-ilp64, Qmkl-ilp64 qmkl-sycl-impl, Qmkl-sycl-impl qopt-assume-no-loop-carried-dep, Qopt-assume-no-loop-carried-dep qopt-dword-index-for-array-of-structs, Qopt-dword-index-for-array-of-structs qopt-dynamic-align, Qopt-dynamic-align qopt-for-throughput, Qopt-for-throughput qopt-mem-layout-trans, Qopt-mem-layout-trans qopt-multiple-gather-scatter-by-shuffles, Qopt-multiple-gather-scatter-by-shuffles qopt-prefetch, Qopt-prefetch qopt-prefetch-distance, Qopt-prefetch-distance qopt-prefetch-loads-only, Qopt-prefetch-loads-only qopt-streaming-stores, Qopt-streaming-stores qopt-zmm-usage, Qopt-zmm-usage qtbb, Qtbb unroll, Qunroll vec, Qvec vec-threshold, Qvec-threshold vecabi, Qvecabi
Code Generation Options x
arch ax, Qax EH fasynchronous-unwind-tables fcf-protection, Qcf-protection fdata-sections, Gw fexceptions ffunction-sections, Gy fomit-frame-pointer Gd GR guard Gv m, Qm m64, Qm64 m80387 march masm mauto-arch, Qauto-arch mbranches-within-32B-boundaries, Qbranches-within-32B-boundaries mintrinsic-promote, Qintrinsic-promote momit-leaf-frame-pointer mtune, tune regcall, Qregcall x, Qx xHost, QxHost
Offload Compilation, OpenMP*, and Parallel Processing Options x
device-math-lib fintelfpga fiopenmp, Qiopenmp flink-huge-device-code fno-sycl-libspirv fopenmp fopenmp-concurrent-host-device-compile, Qopenmp-concurrent-host-device-compile fopenmp-declare-target-scalar-defaultmap, Qopenmp-declare-target-scalar-defaultmap fopenmp-device-code-split, Qopenmp-device-code-split fopenmp-device-lib fopenmp-device-link, Qopenmp-device-link fopenmp-max-parallel-link-jobs, Qopenmp-max-parallel-link-jobs fopenmp-offload-mandatory, Qopenmp-offload-mandatory fopenmp-target-buffers, Qopenmp-target-buffers fopenmp-target-default-sub-group-size, Qopenmp-target-default-sub-group-size fopenmp-target-loopopt, Qopenmp-target-loopopt fopenmp-target-simd, Qopenmp-target-simd fopenmp-targets, Qopenmp-targets fsycl fsycl-add-default-spec-consts-image fsycl-allow-device-dependencies fsycl-dead-args-optimization fsycl-device-code-split fsycl-device-lib fsycl-device-obj fsycl-device-only fsycl-early-optimizations fsycl-enable-function-pointers fsycl-esimd-force-stateless-mem fsycl-explicit-simd fsycl-force-target fsycl-fp64-conv-emu fsycl-help fsycl-host-compiler fsycl-host-compiler-options fsycl-id-queries-fit-in-int fsycl-instrument-device-code fsycl-link fsycl-max-parallel-link-jobs fsycl-optimize-non-user-code fsycl-pstl-offload fsycl-rdc fsycl-remove-unused-external-funcs fsycl-targets fsycl-unnamed-lambda fsycl-use-bitcode ftarget-compile-fast ftarget-export-symbols ftarget-register-alloc-mode, Qtarget-register-alloc-mode nolibsycl qopenmp, Qopenmp qopenmp-link qopenmp-simd, Qopenmp-simd qopenmp-stubs, Qopenmp-stubs reuse-exe Wno-sycl-strict Xopenmp-target Xs Xsycl-target
Interprocedural Optimization Options x
flto ipo, Qipo
Profile Guided Optimization Options x
fprofile-dwo-dir fprofile-ml-use fprofile-sample-generate fprofile-sample-use
Optimization Report Options x
qopt-report, Qopt-report qopt-report-file, Qopt-report-file qopt-report-names, Qopt-report-names qopt-report-phase, Qopt-report-phase qopt-report-stdout, Qopt-report-stdout
Floating-Point Options x
ffp-accuracy, Qfp-accuracy ffp-contract fimf-absolute-error, Qimf-absolute-error fimf-accuracy-bits, Qimf-accuracy-bits fimf-arch-consistency, Qimf-arch-consistency fimf-domain-exclusion, Qimf-domain-exclusion fimf-max-error, Qimf-max-error fimf-precision, Qimf-precision fimf-use-svml, Qimf-use-svml fma, Qfma fp-model, fp fp-speculation, Qfp-speculation ftz, Qftz pc, Qpc
Inlining Options x
fgnu89-inline finline finline-functions inline-forceinline, Qinline-forceinline
Output, Debug, and Precompiled Header Options x
c debug (Linux*) debug (Windows*) Fa fasm-blocks Fe Fo Fp fsystem-debug fverbose-asm g gdwarf grecord-gcc-switches gsplit-dwarf o S use-msasm Y- Yc Yu Zi, Z7, ZI
Preprocessor Options x
B C D dD, QdD dM, QdM E EP FI H, QH I idirafter imacros iprefix iquote isystem iwithprefix iwithprefixbefore M, QM MD, QMD MF, QMF MG, QMG MM, QMM MMD, QMMD MQ, QMQ MT, QMT nostdinc++ P TP U undef X
Component Control Options x
Qoption
Language Options x
ansi fno-gnu-keywords fno-operator-names fno-rtti fpermissive fshort-enums fsyntax-only, Zs funsigned-char, J std, Qstd strict-ansi vd vmg x (type option) Zc Zg Zp
Data Options x
fcommon fkeep-static-consts, Qkeep-static-consts fmaintain-32-byte-stack-align, Qmaintain-32-byte-stack-align fmath-errno fpack-struct fpic fpie fstack-protector fstack-security-check fvisibility fzero-initialized-in-bss, Qzero-initialized-in-bss GA Gs GS mcmodel Qlong-double
Compiler Diagnostic Options x
w W Wabi Wall Wcheck-unicode-security Wcomment Wdeprecated Werror, WX Werror-all Wextra-tokens Wformat Wformat-security Wmain Wmissing-declarations Wmissing-prototypes Wpointer-arith Wreorder Wreturn-type Wshadow Wsign-compare Wstrict-aliasing Wstrict-prototypes Wtrigraphs Wuninitialized Wunknown-pragmas Wunused-function Wunused-variable Wwrite-strings
Compatibility Options x
gcc-toolchain vmv
Linking or Linker Options x
F (Windows*) fixed fortlib fuse-ld l L LD link MD MT nodefaultlibs no-intel-lib, Qno-intel-lib nostartfiles nostdlib pie pthread shared shared-intel shared-libgcc static static-intel static-libgcc static-libstdc++ T u (Linux*) v Wa Wl Wp Xlinker Zl
Miscellaneous Options x
dryrun dumpmachine dumpversion fpreview-breaking-changes help MP nologo save-temps, Qsave-temps showIncludes sox sysroot Tc TC Tp version
Floating-Point Operations x
Programming Tradeoffs in Floating-Point Applications Floating-Point Optimizations Denormal Numbers Floating-Point Environment Set the FTZ and DAZ Flags Tuning Performance IEEE Floating-Point Operations
Attributes x
align align_value allow_cpu_features code_align const cpu_dispatch, cpu_specific target
Libraries x
Create Libraries Use Intel Shared Libraries Manage Libraries Redistribute Libraries When Deploying Applications Resolve References to Shared Libraries Redistributable Library Considerations Intel's Memory Allocator Library SIMD Data Layout Templates Intel® C++ Class Libraries Intel's C++ Asynchronous I/O Extensions for Windows IEEE 754-2008 Binary Floating-Point Conformance Library Intel's Numeric String Conversion Library
SIMD Data Layout Templates x
Function Calls and Containers User-Level Interface Examples
Function Calls and Containers x
Construct an n_container Bounds
User-Level Interface x
SDLT Primitives soa1d_container aos1d_container n_container Bounds Accessors Proxy Objects Number Representation Indexes Convenience and Correctness
aos1d_container x
access_by
n_container x
Layouts Shape make_ n_container template function extent_d template function
Shape x
n_extent_generator
Bounds x
bounds_t sdlt::bounds Template Function n_bounds_t n_bounds_generator bounds_d Template Function
Accessors x
soa1d_container::accessor and aos1d_container::accessor soa1d_container::const_accessor and aos1d_container::const_accessor Accessor Concept
Proxy Objects x
Proxy ConstProxy
Number Representation x
aligned_offset fixed_offset
Indexes x
linear_index n_index_t n_index_generator index_d template function
Convenience and Correctness x
max_val min_val
Examples x
Efficiency with Structure of Arrays Example Complex SDLT Primitive Construction Example Forward Dependency Example Use of Offsets and Methods on a SDLT Primitive Example RGB to YUV Conversion Example
Intel® C++ Class Libraries x
C++ Classes and SIMD Operations Capabilities of C++ SIMD Classes Integer Vector Classes Floating-Point Vector Classes Classes Quick Reference Programming Example Intel's valarray Implementation
Integer Vector Classes x
Terms and Syntax Rules for Operators Assignment Operator Logical Operators Addition and Subtraction Operators Multiplication Operators Shift Operators Comparison Operators Conditional Select Operators Debug Operations Unpack Operators Pack Operators Clear MMX™ State Operator Integer Functions for Intel® Streaming SIMD Extensions Conversions between Fvec and Ivec
Floating-Point Vector Classes x
Fvec Syntax and Notation Data Alignment Conversions Constructors and Initialization Arithmetic Operators Minimum and Maximum Operators Logical Operators Compare Operators Conditional Select Operators for Fvec Classes Cacheability Support Operators Debug Operations Load and Store Operators Unpack Operators Move Mask Operators
Intel's C++ Asynchronous I/O Extensions for Windows x
Intel's C++ Asynchronous I/O Library for Windows Intel's C++ Asynchronous I/O Class for Windows
Intel's C++ Asynchronous I/O Library for Windows x
aio_read aio_write Example for aio_read and aio_write Functions aio_suspend Example for aio_suspend Function aio_error aio_return Example for aio_error and aio_return Functions aio_fsync aio_cancel Example for aio_cancel Function lio_listio Example for lio_listio Function Asynchronous I/O Function Errors
Intel's C++ Asynchronous I/O Class for Windows x
Template Class async_class get_last_operation_id wait get_status get_last_error get_error_operation_id stop_queue resume_queue clear_queue Example for Using async_class Template Class
IEEE 754-2008 Binary Floating-Point Conformance Library x
Intel® IEEE 754-2008 Binary Floating-Point Conformance Library and Usage Function List Homogeneous General-Computational Operations Functions General-Computational Operation Functions Quiet-Computational Operations Functions Signaling-Computational Operations Functions Non-Computational Operations Functions
Intel's Numeric String Conversion Library x
Use Intel's Numeric String Conversion Library Function List
Macros x
ISO Standard Predefined Macros Additional Predefined Macros Use Predefined Macros to Specify Intel® Compilers
Pragmas x
Intel-Specific Pragma Reference Supported OpenMP* Pragmas Pragmas Compatible with Other Compilers
Intel-Specific Pragma Reference x
block_loop/noblock_loop distribute_point inline, noinline, forceinline ivdep loop_count nofusion novector omp target variant dispatch ompx prefetch data prefetch/noprefetch unroll/nounroll unroll_and_jam/nounroll_and_jam vector
Compilation x
Compilation Overview Supported Environment Variables Pass Options to the Linker Specify Alternate Tools Use Configuration Files Use Response Files Global Symbols and Visibility Attributes for Linux* Save Compiler Information in Your Executable Link Debug Information Ahead of Time Compilation Prerequisites Requirements for Accelerators AOT Compilation Supported Options for OpenMP AOT Compilation Supported Options for SYCL Use AOT for the Target Device (Intel® CPUs) Use AOT for Integrated Graphics (Intel® GPU) Use AOT in Microsoft Visual Studio Available GPU Platforms See Also Device Offload Compilation Considerations Use a Third-Party Compiler as a Host Compiler for SYCL Code
Optimization and Programming x
OpenMP* Support SYCL* Support Compiler Sanitizers Intel® oneAPI Level Zero Vectorization Instrumented Profile-Guided Optimization Hardware Profile-Guided Optimization High-Level Optimization Interprocedural Optimization Methods to Optimize Code Size Optimization Reports Compiler Math Library SYCL* Device Library
OpenMP* Support x
Add OpenMP* Support Parallel Processing Model Worksharing Using OpenMP* Control Thread Allocation OpenMP* Library Support OpenMP* Contexts OpenMP* Offloading SPMD/SIMT and SIMD Models OpenMP* Advanced Issues OpenMP* Implementation-Defined Behaviors OpenMP* Examples
OpenMP* Library Support x
OpenMP* Runtime Library Routines Intel® Compiler Extension Routines to OpenMP* OpenMP* Support Libraries Use the OpenMP* Libraries Thread Affinity Interface OpenMP* Memory Spaces and Allocators
OpenMP* Contexts x
OpenMP* Context Selectors Score and Match Context Selectors
SYCL* Support x
SYCL* Extensions Redistribute Your SYCL* Application CUDA* to SYCL* Migration
Intel® oneAPI Level Zero x
Intel® oneAPI Level Zero Switch Intel® oneAPI Level Zero Backend Specification Programming with the Intel® oneAPI Level Zero Backend
Vectorization x
Automatic Vectorization Explicit Vector Programming
Automatic Vectorization x
Vectorization Programming Guidelines Use Automatic Vectorization Vectorization and Loops Loop Constructs
Explicit Vector Programming x
User-Mandated or SIMD Vectorization SIMD-Enabled Functions SIMD-Enabled Function Pointers Function Annotations and the SIMD Directive for Vectorization Explicit SIMD SYCL Extension
Interprocedural Optimization x
Use Interprocedural Optimization Performance Considerations Create a Library from IPO Objects Inline Expansion of Functions
Compiler Math Library x
Use the Compiler Math Library Math Function List Trigonometric Functions Hyperbolic Functions Exponential Functions Special Functions Nearest Integer Functions Remainder Functions Miscellaneous Functions Complex Functions C99 Macros
SYCL* Device Library x
Basic Arithmetic Operations and Simple Math Functions IMF Transcendental Math Functions
Basic Arithmetic Operations and Simple Math Functions x
Simple Integer Math Functions Basic Integer Arithmetic Operations Simple Arithmetic Operations with Rounding Mode Type Casting Functions for Floating-Point Numbers Type Casting Functions for Half-Precision Types Type Casting Functions for bfloat16 Type Simple Half-Precision Arithmetic Math Functions Half-Precision Comparison Functions
IMF Transcendental Math Functions x
IMF Device Library Usage Example IMF Device Library Function List IMF Device Library Trigonometric Functions IMF Device Library Hyperbolic Functions IMF Device Library Exponential Functions IMF Device Library Logarithmic Functions IMF Device Library Power Functions IMF Device Library Special Functions IMF Device Library Rounding Functions IMF Device Library Miscellaneous Functions
Compatibility and Portability x
Standards Conformance GCC Compatibility and Interoperability Microsoft Compatibility Port from Microsoft Visual C++* to the Intel® oneAPI DPC++/C++ Compiler Port from GCC* to the Intel® oneAPI DPC++/C++ Compiler
Port from Microsoft Visual C++* to the Intel® oneAPI DPC++/C++ Compiler x
Modify Your makefile Other Considerations
Port from GCC* to the Intel® oneAPI DPC++/C++ Compiler x
Modify Your makefile Other Considerations
Developer Guide and Reference

Ahead of Time Compilation

Ahead of Time (AOT) Compilation is a helpful feature for your development lifecycle or distribution time. The AOT feature provides the following benefits when you know beforehand what your target device is going to be at application execution time:

  • No additional compilation time is done when running your application.

  • No just-in-time (JIT) bugs encountered due to compilation for the target. Any bugs should be found during AOT and resolved.

  • Your final code, executing on the target device, can be tested as-is before you deliver it to end-users.

A program built with AOT compilation for specific target device(s) will not run on different device(s). You must detect the proper target device at runtime and report an error if the targeted device is not present. The use of exception handling with an asynchronous exception handler is recommended.

SYCL supports AOT compilation for the following targets: Intel® CPUs, Intel® Processor Graphics, and Intel® FPGA. For details on AOT compilation for Intel FPGAs, refer to the Intel® oneAPI FPGA Handbook.

OpenMP supports AOT compilation for the following targets: Intel® Processor Graphics.

For additional information, watch two videos for a quick overview on how to apply the JIT and AOT compilation options:

Prerequisites

To target a GPU with the AOT feature, you must have the OpenCL™ Offline Compiler (OCLOC) tool installed. OCLOC can generate binaries that use OpenCL™ (SYCL only) or the Intel® oneAPI Level Zero (Level Zero) backend.

OCLOC is not packaged with the compiler and must be installed separately. To install OCLOC, you need to install the GPU drivers (whether or not you have an Intel GPU on your system). Refer to the Installing GPU drivers for instructions.

Requirements for Accelerators

GPUs:

  • Intel® UDH Graphics for 11th generation Intel processors or newer

  • Intel® Iris® Xe graphics

  • Intel® Arc™ graphics

  • Intel® Data Center GPU Flex Series

  • Intel® Data Center GPU Max Series

AOT Compilation Supported Options for OpenMP

Use the following options to target a specific device for AOT compilation for OpenMP:

  • -fopenmp-target to specify the device target

  • -Xopenmp-target-backend to pass options to the backend tool

Option -Xopenmp-target-backend is a general device target option. If multiple targets are desired (for example: -fopenmp-targets=spir64,spir64_gen), the options specified with -Xopenmp-target-backend apply to all targets.

For multiple targets, you can add specificity by using, for example, Xopenmp-target-backend=spir64_gen <option>.

When using Ahead of Time (AOT) compilation, the options passed with -Xopenmp-target-backend are not compiler options, but rather options to pass to OCLOC.

To see a list of the options you can pass with -Xopenmp-target-backend when using AOT, specify -fsycl-help=gen on the command line.

AOT Compilation Supported Options for SYCL

Use the following options to target a specific device for AOT compilation for SYCL:

  • -fsycl-target to specify the device target

  • -Xsycl-target-backend to pass options to the backend tool

Option -Xsycl-target-backend is a general device target option. If multiple targets are desired (for example: -fopenmp-targets=spir64_gen,spir64_x86_64), the options specified with -Xsycl-target-backend apply to all targets.

For multiple targets, you can add specificity by using, for example, Xsycl-target-backend=spir64_gen <option>.

When using Ahead of Time (AOT) compilation, the options passed with -Xsycl-target-backend are not compiler options.

To see a list of the options you can pass with -Xsycl-target-backend when using AOT, specify -fsycl-help=gen, -fsycl-help=x86_64, or -fsycl-help=fpga on the command line.

Use AOT for the Target Device (Intel® CPUs)

NOTE:

SYCL compilation is only available with the C/C++ compiler.

However, you can link SYCL-generated objects with the Fortran compiler. The use of -fsycl with ifx allows this, though it is restricted to spir64, spir64_gen, and spir64_x86_64).

Use the following option arguments to specify Intel® CPUs as the target device for AOT compilation:

  • -fsycl-targets=spir64_x86_64

  • -Xsycl-target-backend "-march=<arch>", where <arch> is one of the following:

    Switch Display Name

    avx

    Intel® Advanced Vector Extensions (Intel® AVX)

    avx2

    Intel® Advanced Vector Extensions 2 (Intel® AVX2)

    avx512

    Intel® Advanced Vector Extensions 512 (Intel® AVX-512)

    sse4.2

    Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)

The following examples tell the compiler to generate code that uses Intel® AVX2 instructions:

Linux

icpx -fsycl -fsycl-targets=spir64_x86_64 -Xsycl-target-backend  "-march=avx2" main.cpp

Windows

icx -fsycl /EHsc -fsycl-targets=spir64_x86_64 -Xsycl-target-backend  "-march=avx2" main.cpp

Build an Application with Multiple Source Files for CPU Targeting

NOTE:
This section is for SYCL only.

Compile your normal files (with no SYCL kernels) to create host objects. Then compile the file with the kernel code and link it with the rest of the application.

Linux

The following shows an example of Linux* compilation code: 

icpx -c main.cpp      // This creates the host object that is used below
icpx -c -fsycl-targets=spir64_x86_64 -Xsycl-target-backend "-march=mavx2" mandel.cpp
icpx -fsycl-targets=spir64_x86_64 -Xsycl-target-backend "-march=mavx2" mandel.o main.o

Windows

The following shows an example of Windows* compilation code: 

icx /EHsc -c main.cpp
icx /EHsc -c -fsycl-targets=spir64_x86_64 -Xsycl-target-backend "-march=mavx2" mandel.cpp
icx -fsycl-targets=spir64_x86_64 -Xsycl-target-backend "-march=mavx2" mandel.obj main.obj

Use AOT for Integrated Graphics (Intel® GPU)

Use the following option arguments to specify Intel® GPU as the target device for AOT compilation:

OpenMP

Option -Xopenmp-target-backend is a general-purpose option, any arguments supplied with -Xopenmp-target-backend will be applied to all offline compilation invocations. These are the relevant options and arguments:

  • -Xopenmp-target-backend "-device <arch>", where <arch> is the target device

  • -fopenmp-targets=spir64_gen

  • -fopenmp-device-code-split=<value> to perform an OpenMP device code split. The <value> is:

    • per_kernel, which creates a device code module for each OpenMP kernel

SYCL

Option -Xsycl-target-backend is a general-purpose option, any arguments supplied with -Xsycl-target-backend will be applied to all offline compilation invocations. These are the relevant options and arguments:

  • -Xsycl-target-backend "-device <arch>", where <arch> is the target device

  • -fsycl-targets=spir64_gen

  • -fsycl-device-code-split=<value> option to perform SYCL device code split. The <value> can be:

    • per_kernel, which creates a device code module for each SYCL kernel

    • per_source, which creates a device code module for each source (translation unit)

    • off, which disables device code split

    • auto, which tells the compiler to use a heuristic to select the best way of splitting device code

      This is the default, and it is the same as specifying -fsycl-device-code-split with no <value>.

To see the complete list of supported target device types for your installed version of OCLOC, run: 

ocloc compile --help

To find supported devices look for -device <device_type> in the online help.

If multiple target devices are listed in the compile command, the compiler will compile for each of these targets and create a fat-binary that contains all the device binaries produced this way.

Examples of supported -device patterns:

OpenMP for Linux

  • To compile for a single target, using skl as an example, use: 
    icpx -fiopenmp -fopenmp-targets=spir64_gen -Xopenmp-target-backend "-device skl" vector-add.cpp
  • To compile for two targets, using skl and icllp as examples, use: 
    icpx -fiopenmp -fopenmp-targets=spir64_gen -Xopenmp-target-backend "-device skl,icllp" vector-add.cpp
  • To compile for all the targets known to OCLOC, use: 
    icpx -fiopenmp -fopenmp-targets=spir64_gen -Xopenmp-target-backend "-device *" vector-add.cpp

    Or 

    icpx -fiopenmp -fopenmp-targets=spir64_gen -Xopenmp-target-backend=spir64_gen "-device *" vector-add.cpp

SYCL for Linux

  • To compile for a single target, using skl as an example, use: 
    icpx -fsycl -fsycl-targets=spir64_gen -Xsycl-target-backend "-device skl" vector-add.cpp
  • To compile for two targets, using skl and icllp as examples, use: 
    icpx -fsycl -fsycl-targets=spir64_gen -Xsycl-target-backend "-device skl,icllp" vector-add.cpp
  • To compile for all the targets known to OCLOC, use: 
    icpx -fsycl -fsycl-targets=spir64_gen -Xsycl-target-backend "-device *" vector-add.cpp
  • To pass multiple options to use OCLOC, use:
    • -Xs options: 
      icpx -fsycl -fsycl-targets=spir64_gen -Xs "-device tgllp --format zebin -options <-user-option1> -options <-user-option2>" vector-add.cpp
    • -Xsycl-target-backend options: 
      icpx -fsycl -fsycl-targets=spir64_gen -Xsycl-target-backend=spir64_gen "-device tgllp --format zebin -options <-user-option1> -options <-user-option2>" vector-add.cpp

SYCL for Windows

  • To compile for a single target, using skl as an example, use: 
    icx -fsycl /EHsc -fsycl-targets=spir64_gen -Xsycl-target-backend "-device skl" vector-add.cpp
  • To compile for two targets, using skl and icllp as examples, use: 
    icx -fsycl /EHsc -fsycl-targets=spir64_gen -Xsycl-target-backend "-device skl,icllp" vector-add.cpp
  • To compile for all the targets known to OCLOC, use: 
    icx -fsycl /EHsc -fsycl-targets=spir64_gen -Xsycl-target-backend "-device *" vector-add.cpp

    Or 

    icx -fsycl /EHsc -fsycl-targets=spir64_gen -Xsycl-target-backend=spir64_gen "-device *" vector-add.cpp

Build an Application with Multiple Source Files for GPU Targeting

Compile your normal files (with no SYCL kernels) to create host objects. Then compile the file with the kernel code and link it with the rest of the application.

Linux

icpx -c main.cpp
icpx -fsycl -fsycl-targets=spir64_gen -Xsycl-target-backend=spir64_gen "-device *" mandel.o main.o

Windows

icx /c main.cpp
icx -fsycl /EHsc -fsycl-targets=spir64_gen -Xsycl-target-backend=spir64_gen "-device *" mandel.cpp main.obj

Use AOT in Microsoft Visual Studio

NOTE:
This section is for SYCL only.

You can use Microsoft Visual Studio for compiling and linking. Set the following flags to use AOT compilation for CPU or GPU:

CPU:

  • To compile, in the dialog box, select: Configuration Properties > DPC++ > General > Specify SYCL offloading targets for AOT compilation.
  • To link, in the dialog box, select: Configuration Properties > Linker > General > Specify CPU Target Device for AOT compilation.

GPU:

  • To compile, in the dialog box, select: Configuration Properties > DPC++ > General > Specify SYCL offloading targets for AOT compilation.
  • To link, in the dialog box, select: Configuration Properties > Linker > General > Specify GPU Target Device for AOT compilation.

Available GPU Platforms

GPU Model Name Vertical Segment Product Code Name AOT Compilation Device Name Compatible Targets

Intel® Arc™ graphics 140V (Integrated in Intel® Core™ Ultra 9 Processor 288V, Intel® Core™ Ultra 7 Processor 268V, Intel® Core™ Ultra 7 Processor 266V, Intel® Core™ Ultra 7 Processor 258V, Intel® Core™ Ultra 7 Processor 256V)

Mobile

Lunar Lake

lnl-m

 

Intel® Arc™ graphics 130V (Integrated in Intel® Core™ Ultra 5 Processor 238V, Intel® Core™ Ultra 5 Processor 236V, Intel® Core™ Ultra 5 Processor 228V, Intel® Core™ Ultra 5 Processor 226V)

Mobile

Lunar Lake

lnl-m

 

Intel® Arc™ graphics (Integrated in Intel® Core™ Ultra 9 Processor 185H, Intel® Core™ Ultra 7 Processor 165H, Intel® Core™ Ultra 7 Processor 155H, Intel® Core™ Ultra 5 Processor 135H, Intel® Core™ Ultra 5 Processor 125H)

Mobile

Meteor Lake-H

mtl-h

mtl

Intel® Arc™ graphics (Integrated in Intel® Core™ Ultra 7 Processor 165HL, Intel® Core™ Ultra 7 Processor 155HL, Intel® Core™ Ultra 5 Processor 135HL, Intel® Core™ Ultra 5 Processor 125HL)

Embedded

Meteor Lake-H

mtl-h

mtl

Intel® Graphics (Integrated in Intel® Core™ Ultra 7 Processor 165U, Intel® Core™ Ultra 7 Processor 164U, Intel® Core™ Ultra 7 Processor 155U, Intel® Core™ Ultra 5 Processor 135U, Intel® Core™ Ultra 5 Processor 134U, Intel® Core™ Ultra 5 Processor 125U)

Mobile

Meteor Lake-U, Arrow Lake-U/S

mtl-u (or arl-u, arl-s)

mtl

Intel® Graphics (Integrated in Intel® Core™ Ultra 7 Processor 165UL, Intel® Core™ Ultra 7 Processor 155UL, Intel® Core™ Ultra 5 Processor 135UL, Intel® Core™ Ultra 5 Processor 125UL, Intel® Core™ Ultra 3 Processor 105UL)

Embedded

Meteor Lake-U, Arrow Lake-U/S

mtl-u (or arl-u, arl-s)

mtl

Intel® MAX® 1550, Intel® MAX® 1100

Data Center

Ponte Vecchio

pvc

 

Intel® Flex 170

Data Center

Arctic Sound

ats-m150

dg2

Intel® Flex 140

Data Center

Arctic Sound

ats-m75

dg2

Intel® Arc™ A770, Intel® Arc™ A750, Intel® Arc™ A580

Desktop

Alchemist

acm-g10 (or dg2-g10, ats-m150)

dg2

Intel® Arc™ A770M, Intel® Arc™ A730M, Intel® Arc™ A550M

Mobile

Alchemist

acm-g10 (or dg2-g10, ats-m150)

dg2

Intel® Arc™ A380, Intel® Arc™ A310, Intel® Arc™ Pro A40/A50

Desktop

Alchemist

acm-g11 (or dg2-g11, ats-m75)

dg2

Intel® Arc™ A370M, Intel® Arc™ A350M, Intel® Arc™ Pro A30M

Mobile

Alchemist

acm-g11 (or dg2-g11, ats-m75)

dg2

Intel® Arc™ A380E, Intel® Arc™ A370E, Arc™ A350E, Intel® Arc™ A310E

Embedded

Alchemist

acm-g11 (or dg2-g11, ats-m75)

dg2

Intel® UHD Graphics

Mobile

Alder Lake-N

adl-n

 

Intel® UHD Graphics, Intel® Iris® Xe graphics

Mobile

Alder Lake-P

adl-p

 

Intel® UHD Graphics 770/730/710

Mobile

Alder Lake-S

adl-s

 

Intel® UHD Graphics 617/615

Mobile

Amber Lake

aml

 

Intel® HD Graphics, Intel® HD Graphics 505/500

Mobile

Apollo Lake, Broxton

apl (or bxt)

 

Intel® Iris® Plus graphics 655/645, Intel® UHD Graphics 630/610/P630

Mobile

Coffee Lake

cfl

 

Intel® UHD Graphics

Mobile

Comet Lake

cml

 

Intel® Iris® Xe MAX graphics, Intel® Iris® Xe graphics, Intel® Iris® Xe MAX 100, Intel® Server GPU SG-18M

Mobile/Server

DG1

dg1

 

Intel® UHD Graphics

Mobile

Elkhart Lake, Jasper Lake

ehl jsl

 

Intel® UHD Graphics 605/600

Mobile

Gemini Lake

glk

 

Intel® HD Graphics, Intel® UHD Graphics, Intel® Iris® Plus Graphics

Mobile

Ice Lake

icllp

 

Intel® HD Graphics 635, Intel® Iris® Plus Graphics 650/640, Intel® HD Graphics 630/620/P630/615/610, Intel® UHD Graphics 617/615

Mobile

Kaby Lake

kbl

 

Intel® UHD Graphics 750/730/P750

Mobile

Rocket Lake

rkl

 

Intel® Iris® Xe Graphics, Intel® UHD Graphics

Mobile

Raptor Lake-P

rpl-p

 

Intel® UHD Graphics 770/730/710

Mobile

Raptor Lake-S

rpl-s

 

Intel® HD Graphics 535/530/520/515/510/P530, Intel® Iris® Pro Graphics 580/P580, Intel® Iris® Graphics 555/550/540/P555

Mobile

Intel® microarchitecture code name Skylake

skl

 

Intel® UHD Graphics, Intel® Iris® Xe Graphics

Mobile

Tiger Lake

tgllp

 

Intel® UHD Graphics, Intel® UHD Graphics 620

Mobile

Whiskey Lake

whl

 
Parent topic: Compilation

See Also

fopenmp-targets compiler option
fsycl-targets compiler option
Xsycl-target compiler option
Xopenmp-target compiler option
Xs compiler option
Level Two Title