Visible to Intel only — GUID: GUID-57EE2043-5E2B-4AEA-8114-4900B401053B
Visible to Intel only — GUID: GUID-57EE2043-5E2B-4AEA-8114-4900B401053B
fsycl-link
Tells the compiler to perform a partial link of device binaries to be used with Field Programmable Gate Array (FPGA).
Syntax
Linux: |
-fsycl-link[=value] |
Windows: |
-fsycl-link[=value] |
Arguments
value |
Can be one of the following:
image takes much longer to generate than does early. |
Default
OFF |
No partial link of device binaries is performed. |
Description
This option tells the compiler to perform a partial link of device binaries to be used with FPGA.
This partial link is then wrapped by the offload wrapper, allowing the device binaries to be linked by the host compiler or linker.
If you do not specify a value, the following occurs:
When used with just -fsycl (-fsycl -fsycl-link), the driver will generate a host linkable device object.
When also used with -fintelfpga (-fsycl -fintelfpga -fsycl-link), the behavior is the same as specifying -fsycl-link=early.
When using this option, you must also specify option -fsycl.
For information about available SYCL drivers, refer to Invoke the Compiler.
When SYCL offloading is enabled, this option only applies to device-specific compilation.
IDE Equivalent
Visual Studio: Linker > General > Generate partially linked device object to be used with the host link
Eclipse: Linker > General > Generate partially linked device object to be used with the host link
Alternate Options
None