Intel® C++ Compiler Classic Developer Guide and Reference

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ID 767249
Date 12/16/2022
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Document Table of Contents
Document Table of Contents x
Intel® C++ Compiler Classic Developer Guide and Reference
Intel® C++ Compiler Classic Developer Guide and Reference x
Intel® C++ Compiler Classic Introduction Compiler Setup Compiler Reference Compilation Optimization and Programming Compatibility and Portability Notices and Disclaimers
Intel® C++ Compiler Classic Introduction x
Get Help and Support Related Information
Compiler Setup x
Use the Command Line Use Eclipse* Use Microsoft Visual Studio* Use Xcode* (macOS)
Use the Command Line x
Specify Component Locations Invoke the Compiler Use the Command Line on Windows File Extensions Use Makefiles for Compilation Use Compiler Options Specify Compiler Files Convert Projects to Use a Selected Compiler
Use Eclipse* x
Add the Compiler to Eclipse* Multi-Version Compiler Support Use Cheat Sheets Create a Simple Eclipse Project Makefiles Use Intel Libraries with Eclipse*
Use Microsoft Visual Studio* x
Create a New Project Use the Intel® C++ Compiler Classic Select the Compiler Version Specify a Base Platform Toolset Use Property Pages Use Intel® Libraries with Microsoft Visual Studio* Include MPI Support Use Guided Auto Parallelism in Microsoft Visual Studio* Use Code Coverage in Microsoft Visual Studio* Use Profile Guided Optimization in Microsoft Visual Studio* Optimization Reports Dialog Box Help
Dialog Box Help x
Options: Compilers dialog box Use Intel® C++ Compiler Classic dialog box Options: Intel Libraries for oneAPI dialog box Options: Converter dialog box Options: Optimization Reports dialog box Options: Guided Auto Parallelism dialog box Configure Analysis dialog box Options: Profile Guided Optimization (PGO) dialog box Profile Guided Optimization dialog box Options: Code Coverage dialog box Code Coverage dialog box Code Coverage Settings dialog box
Use Xcode* (macOS) x
Create an Xcode* Project Select the Intel® Compiler Build the Target Set Compiler Options Run the Executable Use Intel Libraries with Xcode*
Compiler Reference x
C/C++ Calling Conventions Compiler Options Floating-Point Operations Attributes Intrinsics Libraries Macros Pragmas Error Handling
Compiler Options x
Alphabetical Option List General Rules for Compiler Options What Appears in the Compiler Option Descriptions Optimization Options Code Generation Options Interprocedural Optimization Options Advanced Optimization Options Profile Guided Optimization Options Optimization Report Options OpenMP* Options and Parallel Processing Options Floating-Point Options Inlining Options Output, Debug, and Precompiled Header Options Preprocessor Options Component Control Options Language Options Data Options Compiler Diagnostic Options Compatibility Options Linking or Linker Options Miscellaneous Options Deprecated and Removed Compiler Options Display Option Information Alternate Compiler Options Portability and GCC-compatible Warning Options
Optimization Options x
falias, Oa fast fbuiltin, Oi fdefer-pop ffnalias, Ow foptimize-sibling-calls fprotect-parens, Qprotect-parens GF nolib-inline O Od Ofast Os Ot Ox
Code Generation Options x
arch ax, Qax EH fasynchronous-unwind-tables fcf-protection, Qcf-protection fdata-sections, Gw fexceptions ffunction-sections, Gy fomit-frame-pointer, Oy Gd Gr GR guard Gv Gz hotpatch m m32, m64, Qm32, Qm64 m80387 march masm mauto-arch, Qauto-arch mbranches-within-32B-boundaries, Qbranches-within-32B-boundaries mconditional-branch, Qconditional-branch minstruction, Qinstruction momit-leaf-frame-pointer mregparm mregparm-version mstringop-inline-threshold, Qstringop-inline-threshold mstringop-strategy, Qstringop-strategy mtune, tune Qcxx-features Qpatchable-addresses Qsafeseh regcall, Qregcall x, Qx xHost, QxHost
Interprocedural Optimization Options x
ffat-lto-objects ip, Qip ip-no-inlining, Qip-no-inlining ip-no-pinlining, Qip-no-pinlining ipo, Qipo ipo-c, Qipo-c ipo-jobs, Qipo-jobs ipo-S, Qipo-S ipo-separate, Qipo-separate
Advanced Optimization Options x
alias-const, Qalias-const ansi-alias, Qansi-alias ansi-alias-check, Qansi-alias-check complex-limited-range, Qcomplex-limited-range fargument-alias, Qalias-args fargument-noalias-global ffreestanding, Qfreestanding fjump-tables ftls-model funroll-all-loops guide, Qguide guide-data-trans, Qguide-data-trans guide-file, Qguide-file guide-file-append, Qguide-file-append guide-opts, Qguide-opts guide-par, Qguide-par guide-vec, Qguide-vec ipp-link, Qipp-link qdaal, Qdaal qipp, Qipp qmkl, Qmkl qmkl-ilp64, Qmkl-ilp64 qopt-args-in-regs, Qopt-args-in-regs qopt-assume-no-loop-carried-dep, Qopt-assume-no-loop-carried-dep qopt-assume-safe-padding, Qopt-assume-safe-padding qopt-block-factor, Qopt-block-factor qopt-calloc qopt-class-analysis, Qopt-class-analysis qopt-dynamic-align, Qopt-dynamic-align qopt-jump-tables, Qopt-jump-tables qopt-malloc-options qopt-matmul, Qopt-matmul qopt-mem-layout-trans, Qopt-mem-layout-trans qopt-multi-version-aggressive, Qopt-multi-version-aggressive qopt-multiple-gather-scatter-by-shuffles, Qopt-multiple-gather-scatter-by-shuffles qopt-prefetch, Qopt-prefetch qopt-prefetch-distance, Qopt-prefetch-distance qopt-prefetch-issue-excl-hint, Qopt-prefetch-issue-excl-hint qopt-ra-region-strategy, Qopt-ra-region-strategy qopt-streaming-stores, Qopt-streaming-stores qopt-subscript-in-range, Qopt-subscript-in-range qopt-zmm-usage, Qopt-zmm-usage qoverride-limits, Qoverride-limits qtbb, Qtbb Qvla scalar-rep, Qscalar-rep simd, Qsimd simd-function-pointers, Qsimd-function-pointers unroll, Qunroll unroll-aggressive, Qunroll-aggressive use-intel-optimized-headers, Quse-intel-optimized-headers vec, Qvec vec-guard-write, Qvec-guard-write vec-threshold, Qvec-threshold vecabi, Qvecabi
Profile Guided Optimization Options x
finstrument-functions, Qinstrument-functions fnsplit, Qfnsplit Gh GH p prof-data-order, Qprof-data-order prof-dir, Qprof-dir prof-file, Qprof-file prof-func-groups prof-func-order, Qprof-func-order prof-gen, Qprof-gen prof-gen-sampling prof-hotness-threshold, Qprof-hotness-threshold prof-src-dir, Qprof-src-dir prof-src-root, Qprof-src-root prof-src-root-cwd, Qprof-src-root-cwd prof-use, Qprof-use prof-use-sampling prof-value-profiling, Qprof-value-profiling Qcov-dir Qcov-file Qcov-gen
Optimization Report Options x
qopt-report, Qopt-report qopt-report-annotate, Qopt-report-annotate qopt-report-annotate-position, Qopt-report-annotate-position qopt-report-embed, Qopt-report-embed qopt-report-file, Qopt-report-file qopt-report-filter, Qopt-report-filter qopt-report-format, Qopt-report-format qopt-report-help, Qopt-report-help qopt-report-names, Qopt-report-names qopt-report-per-object, Qopt-report-per-object qopt-report-phase, Qopt-report-phase qopt-report-routine, Qopt-report-routine
OpenMP* Options and Parallel Processing Options x
device-math-lib fmpc-privatize fopenmp-device-lib par-affinity, Qpar-affinity par-loops, Qpar-loops par-num-threads, Qpar-num-threads par-runtime-control, Qpar-runtime-control par-schedule, Qpar-schedule par-threshold, Qpar-threshold parallel, Qparallel parallel-source-info, Qparallel-source-info qopenmp, Qopenmp qopenmp-lib, Qopenmp-lib qopenmp-link qopenmp-simd, Qopenmp-simd qopenmp-stubs, Qopenmp-stubs qopenmp-threadprivate, Qopenmp-threadprivate Qpar-adjust-stack
Floating-Point Options x
fast-transcendentals, Qfast-transcendentals fimf-absolute-error, Qimf-absolute-error fimf-accuracy-bits, Qimf-accuracy-bits fimf-arch-consistency, Qimf-arch-consistency fimf-domain-exclusion, Qimf-domain-exclusion fimf-force-dynamic-target, Qimf-force-dynamic-target fimf-max-error, Qimf-max-error fimf-precision, Qimf-precision fimf-use-svml, Qimf-use-svml fma, Qfma fp-model, fp fp-port, Qfp-port fp-speculation, Qfp-speculation fp-stack-check, Qfp-stack-check fp-trap, Qfp-trap fp-trap-all, Qfp-trap-all ftz, Qftz Ge mp1, Qprec pc, Qpc prec-div, Qprec-div prec-sqrt, Qprec-sqrt qsimd-honor-fp-model, Qsimd-honor-fp-model qsimd-serialize-fp-reduction, Qsimd-serialize-fp-reduction rcd, Qrcd
Inlining Options x
fgnu89-inline finline finline-functions finline-limit inline-calloc, Qinline-calloc inline-factor, Qinline-factor inline-forceinline, Qinline-forceinline inline-level, Ob inline-max-per-compile, Qinline-max-per-compile inline-max-per-routine, Qinline-max-per-routine inline-max-size, Qinline-max-size inline-max-total-size, Qinline-max-total-size inline-min-caller-growth, Qinline-min-caller-growth inline-min-size, Qinline-min-size Qinline-dllimport
Output, Debug, and Precompiled Header Options x
c debug (Linux* and macOS) debug (Windows*) Fa FA fasm-blocks FC fcode-asm Fd FD Fe feliminate-unused-debug-types, Qeliminate-unused-debug-types femit-class-debug-always fmerge-constants fmerge-debug-strings Fo Fp FR fsource-asm ftrapuv, Qtrapuv fverbose-asm g gdwarf Gm grecord-gcc-switches gsplit-dwarf map-opts, Qmap-opts o pch pch-create pch-dir pch-use pdbfile print-multi-lib Qpchi Quse-msasm-symbols RTC S use-asm, Quse-asm use-msasm V (Windows*) Y- Yc Yd Yu Zi, Z7, ZI Zo
Preprocessor Options x
A, QA B C D dD, QdD dM, QdM dN, QdN E EP FI gcc, gcc-sys gcc-include-dir H, QH I I- icc, Qicl idirafter imacros iprefix iquote isystem iwithprefix iwithprefixbefore Kc++, TP M, QM MD, QMD MF, QMF MG, QMG MM, QMM MMD, QMMD MP MQ MT, QMT nostdinc++ P pragma-optimization-level u (Windows*) U undef X
Component Control Options x
Qinstall Qlocation Qoption
Language Options x
ansi check early-template-check fblocks ffriend-injection fno-gnu-keywords fno-implicit-inline-templates fno-implicit-templates fno-operator-names fno-rtti fnon-lvalue-assign fpermissive fshort-enums fsyntax-only ftemplate-depth, Qtemplate-depth funsigned-bitfields funsigned-char GZ H (Windows*) help-pragma, Qhelp-pragma intel-extensions, Qintel-extensions J restrict, Qrestrict std, Qstd strict-ansi vd vmb vmg vmm vms x (type option) Za Zc Ze Zg Zp Zs
Data Options x
align auto-ilp32, Qauto-ilp32 auto-p32 check-pointers, Qcheck-pointers check-pointers-dangling, Qcheck-pointers-dangling check-pointers-mpx, Qcheck-pointers-mpx check-pointers-narrowing, Qcheck-pointers-narrowing check-pointers-undimensioned, Qcheck-pointers-undimensioned falign-functions, Qfnalign falign-loops, Qalign-loops falign-stack fcommon fextend-arguments, Qextend-arguments fkeep-static-consts, Qkeep-static-consts fmath-errno fminshared fmudflap fpack-struct fpascal-strings fpic fpie freg-struct-return fstack-protector fstack-security-check fvisibility fvisibility-inlines-hidden fzero-initialized-in-bss, Qzero-initialized-in-bss GA Gs GS GT homeparams malign-double malign-mac68k malign-natural malign-power mcmodel mdynamic-no-pic mlong-double no-bss-init, Qnobss-init noBool Qlong-double Qsfalign
Compiler Diagnostic Options x
diag, Qdiag diag-dump, Qdiag-dump diag-enable=power, Qdiag-enable:power diag-error-limit, Qdiag-error-limit diag-file, Qdiag-file diag-file-append, Qdiag-file-append diag-id-numbers, Qdiag-id-numbers diag-once, Qdiag-once fnon-call-exceptions traceback w w, W Wabi Wall Wbrief Wcheck Wcheck-unicode-security Wcomment Wcontext-limit, Qcontext-limit wd, Qwd Wdeprecated we, Qwe Weffc++, Qeffc++ Werror, WX Werror-all Wextra-tokens Wformat Wformat-security Wic-pointer Winline WL Wmain Wmissing-declarations Wmissing-prototypes wn, Qwn Wnon-virtual-dtor wo, Qwo Wp64 Wpch-messages Wpointer-arith Wport wr, Qwr Wremarks Wreorder Wreturn-type Wshadow Wsign-compare Wstrict-aliasing Wstrict-prototypes Wtrigraphs Wuninitialized Wunknown-pragmas Wunused-function Wunused-variable ww, Qww Wwrite-strings
Compatibility Options x
clang-name clangxx-name fabi-version fms-dialect gcc-name gnu-prefix gxx-name Qgcc-dialect Qms Qvc stdlib vmv
Linking or Linker Options x
Bdynamic Bstatic Bsymbolic Bsymbolic-functions cxxlib dynamic-linker dynamiclib F (Windows*) F (macOS) fixed Fm fuse-ld l L LD link MD MT no-libgcc nodefaultlibs no-intel-lib, Qno-intel-lib nostartfiles nostdlib pie pthread shared shared-intel shared-libgcc static static-intel static-libgcc static-libstdc++ staticlib T u (Linux*) v Wa Wl Wp Xlinker Zl
Miscellaneous Options x
bigobj dryrun dumpmachine dumpversion global-hoist, Qglobal-hoist help intel-freestanding intel-freestanding-target-os MP-force multibyte-chars, Qmultibyte-chars multiple-processes, MP nologo print-sysroot save-temps, Qsave-temps showIncludes sox sysroot Tc TC Tp V version watch
Floating-Point Operations x
Programming Tradeoffs in Floating-Point Applications Floating-point Optimizations Use the -fp-model, /fp Option Denormal Numbers Floating-Point Environment Set the FTZ and DAZ Flags Checking the Floating-point Stack State Tuning Performance IEEE Floating-point Operations
Attributes x
align align_value avoid_false_share code_align concurrency_safe const cpu_dispatch, cpu_specific mpx target vector vector_variant
Intrinsics x
Details about Intrinsics Naming and Usage Syntax References Intrinsics for All Intel® Architectures Data Alignment, Memory Allocation Intrinsics, and Inline Assembly Intrinsics for Managing Extended Processor States and Registers Intrinsics for the Short Vector Random Number Generator Library Intrinsics for Instruction Set Architecture (ISA) Instructions Intrinsics for Intel® Advanced Matrix Extensions (Intel(R) AMX) Instructions Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) BF16 Instructions Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) 4VNNIW Instructions Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) 4FMAPS Instructions Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) VPOPCNTDQ Instructions Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Additional Instructions Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Instructions Intrinsics for Later Generation Intel® Core™ Processor Instruction Extensions Intrinsics for Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intrinsics for Intel® Advanced Vector Extensions Intrinsics for Intel® Streaming SIMD Extensions 4 (Intel® SSE4) Intrinsics for Intel® Supplemental Streaming SIMD Extensions 3 (SSSE3) Intrinsics for Intel® Streaming SIMD Extensions 3 (Intel® SSE3) Intrinsics for Intel® Streaming SIMD Extensions 2 (Intel® SSE2) Intrinsics for Intel® Streaming SIMD Extensions (Intel® SSE) Intrinsics for MMX™ Technology Intrinsics for Advanced Encryption Standard Implementation Intrinsics for Converting Half Floats Intrinsics for Short Vector Math Library Operations (SVML)
Intrinsics for All Intel® Architectures x
Integer Arithmetic Intrinsics Floating-point Intrinsics String and Block Copy Intrinsics Miscellaneous Intrinsics _may_i_use_cpu_feature _allow_cpu_features
Data Alignment, Memory Allocation Intrinsics, and Inline Assembly x
Alignment Support Allocating and Freeing Aligned Memory Blocks Inline Assembly
Intrinsics for Managing Extended Processor States and Registers x
Intrinsics for Reading and Writing the Content of Extended Control Registers Intrinsics for Saving and Restoring the Extended Processor States
Intrinsics for Reading and Writing the Content of Extended Control Registers x
_xgetbv() _xsetbv()
Intrinsics for Saving and Restoring the Extended Processor States x
_fxsave() _fxsave64() _fxrstor() _fxrstor64() _xsave()/_xsavec()/_xsaves() _xsave64()/ _xsavec64()/ _xsaves64() _xsaveopt() _xsaveopt64() _xrstor()/xrstors() _xrstor64()/xrstors64()
Intrinsics for the Short Vector Random Number Generator Library x
Data Types and Calling Conventions Usage Model Engine Initialization and Finalization Distribution Initialization and Finalization Random Values Generation Service Routines
Engine Initialization and Finalization x
svrng_new_rand0_engine/svrng_new_rand0_ex svrng_new_rand_engine/svrng_new_rand_ex svrng_new_mcg31m1_engine/svrng_new_mcg31m1_ex svrng_new_mcg59_engine/svrng_new_mcg59_ex svrng_new_mt19937_engine/svrng_new_mt19937_ex svrng_delete_engine
Distribution Initialization and Finalization x
svrng_new_uniform_distribution_[int|float|double]/svrng_update_uniform_distribution_[int|float|double] svrng_new_normal_distribution_[float|double]/svrng_update_normal_distribution_[float|double] svrng_delete_distribution
Random Values Generation x
svrng_generate[1|2|4|8|16|32]_[uint|ulong] svrng_generate[1|2|4|8|16|32]_[int|float|double]
Service Routines x
Parallel Computation Support Error Handling
Parallel Computation Support x
svrng_copy_engine svrng_skipahead_engine svrng_leapfrog_engine
Error Handling x
svrng_set_status svrng_get_status
Intrinsics for Instruction Set Architecture (ISA) Instructions x
SERIALIZE TSXLDTRK
SERIALIZE x
_serialize
TSXLDTRK x
_xresldtrk _xsusldtrk
Intrinsics for Intel® Advanced Matrix Extensions (Intel(R) AMX) Instructions x
Intrinsic for Intel® Advanced Matrix Extensions AMX-BF16 Instructions Intrinsics for Intel® Advanced Matrix Extensions AMX-INT8 Instructions Intrinsics for Intel(R) Advanced Matrix Extensions AMX-TILE Instructions
Intrinsic for Intel® Advanced Matrix Extensions AMX-BF16 Instructions x
_tile_dpbf16ps
Intrinsics for Intel® Advanced Matrix Extensions AMX-INT8 Instructions x
_tile_dpbssd _tile_dpbsud _tile_dpbusd _tile_dpbuud
Intrinsics for Intel(R) Advanced Matrix Extensions AMX-TILE Instructions x
_tile_loadconfig _tile_loadd _tile_release _tile_storeconfig _tile_stored _tile_stream_loadd _tile_zero
Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Additional Instructions x
Intrinsics for Arithmetic Operations Intrinsics for Bit Manipulation Operations Intrinsics for Comparison Operations Intrinsics for Conversion Operations Intrinsics for Load Operations Intrinsics for Logical Operations Intrinsics for Miscellaneous Operations Intrinsics for Move Operations Intrinsics for Set Operations Intrinsics for Shift Operations Intrinsics for Store Operations
Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Instructions x
Intrinsics for Arithmetic Operations Intrinsics for Blend Operations Intrinsics for Bit Manipulation Operations Intrinsics for Broadcast Operations Intrinsics for Comparison Operations Intrinsics for Compression Operations Intrinsics for Conversion Operations Intrinsics for Expand and Load Operations Intrinsics for Gather and Scatter Operations Intrinsics for Insert and Extract Operations Intrinsics for Load and Store Operations Intrinsics for Miscellaneous Operations Intrinsics for Move Operations Intrinsics for Pack and Unpack Operations Intrinsics for Permutation Operations Intrinsics for Reduction Operations Intrinsics for Set Operations Intrinsics for Shuffle Operations Intrinsics for Test Operations Intrinsics for Typecast Operations Intrinsics for Vector Mask Operations
Intrinsics for Arithmetic Operations x
Intrinsics for Addition Operations Intrinsics for Determining Minimum and Maximum Values Intrinsics for FP Fused Multiply-Add (FMA) Operations Intrinsics for Multiplication Operations Intrinsics for Subtraction Operations Intrinsics for Other Mathematics Operations
Intrinsics for Addition Operations x
Intrinsics for FP Addition Operations Intrinsics for Integer Addition Operations
Intrinsics for Determining Minimum and Maximum Values x
Intrinsics for Determining Minimum and Maximum FP Values Intrinsics for Determining Minimum and Maximum Integer Values
Intrinsics for Multiplication Operations x
Intrinsics for FP Multiplication Operations Intrinsics for Integer Multiplication Operations
Intrinsics for Subtraction Operations x
Intrinsics for FP Subtraction Operations Intrinsics for Integer Subtraction Operations
Intrinsics for Other Mathematics Operations x
Intrinsics for FP Division Operations Intrinsics for Absolute Value Operations Intrinsics for Scale Operations
Intrinsics for Bit Manipulation Operations x
Intrinsics for Integer Bit Manipulation and Conflict Detection Operations Intrinsics for Bitwise Logical Operations Intrinsics for Integer Bit Rotation Operations Intrinsics for Integer Bit Shift Operations
Intrinsics for Broadcast Operations x
Intrinsics for FP Broadcast Operations Intrinsics for Integer Broadcast Operations
Intrinsics for Comparison Operations x
Intrinsics for FP Comparison Operations Intrinsics for Integer Comparison Operations
Intrinsics for Conversion Operations x
Intrinsics for FP Conversion Operations Intrinsics for Integer Conversion Operations
Intrinsics for Expand and Load Operations x
Intrinsics for FP Expand and Load Operations Intrinsics for Integer Expand and Load Operations
Intrinsics for Gather and Scatter Operations x
Intrinsics for FP Gather and Scatter Operations Intrinsics for Integer Gather and Scatter Operations
Intrinsics for Insert and Extract Operations x
Intrinsics for FP Insert and Extract Operations Intrinsics for Integer Insert and Extract Operations
Intrinsics for Load and Store Operations x
Intrinsics for FP Loads and Store Operations Intrinsics for Integer Load and Store Operations
Intrinsics for Miscellaneous Operations x
Intrinsics for Miscellaneous FP Operations Intrinsics for Miscellaneous Integer Operations
Intrinsics for Move Operations x
Intrinsics for FP Move Operations Intrinsics for Integer Move Operations
Intrinsics for Pack and Unpack Operations x
Intrinsics for FP Pack and Unpack Operations Intrinsics for Integer Pack and Unpack Operations
Intrinsics for Permutation Operations x
Intrinsics for FP Permutation Operations Intrinsics for Integer Permutation Operations
Intrinsics for Reduction Operations x
Intrinsics for FP Reduction Operations Intrinsics for Integer Reduction Operations
Intrinsics for Shuffle Operations x
Intrinsics for FP Shuffle Operations Intrinsics for Integer Shuffle Operations
Intrinsics for Later Generation Intel® Core™ Processor Instruction Extensions x
Intrinsics for 3rd Generation Intel® Core™ Processor Instruction Extensions Intrinsics for 4th Generation Intel® Core™ Processor Instruction Extensions Intrinsics for Converting Half Floats that Map to 3rd Generation Intel® Core™ Processor Instructions Intrinsics that Generate Random Numbers of 16/32/64 Bit Wide Random Integers Intrinsics for Multi-Precision Arithmetic Intrinsics that Allow Reading from and Writing to the FS Base and GS Base Registers
Intrinsics for Converting Half Floats that Map to 3rd Generation Intel® Core™ Processor Instructions x
_mm_cvtph_ps() _mm256_cvtph_ps() <span class='option'> _mm_cvtps_ph()</span> _mm256_cvtps_ph()
Intrinsics that Generate Random Numbers of 16/32/64 Bit Wide Random Integers x
<span class='option'> _rdrand16_step()</span>, <span class='option'> _rdrand32_step()</span>, <span class='option'> _rdrand64_step()</span> _rdseed16_step/ _rdseed32_step/ _rdseed64_step
Intrinsics for Multi-Precision Arithmetic x
_addcarry_u32(), _addcarry_u64() _addcarryx_u32(), _addcarryx_u64() _subborrow_u32(), _subborrow_u64()
Intrinsics that Allow Reading from and Writing to the FS Base and GS Base Registers x
_readfsbase_u32(), _readfsbase_u64() <span class='option'> _readgsbase_u32()</span>, <span class='option'>_readgsbase_u64()</span> _writefsbase_u32(), _writefsbase_u64() _writegsbase_u32(), _writegsbase_u64()
Intrinsics for Intel® Advanced Vector Extensions 2 (Intel® AVX2) x
Intrinsics for Arithmetic Operations Intrinsics for Arithmetic Shift Operations Intrinsics for Blend Operations Intrinsics for Bitwise Operations Intrinsics for Broadcast Operations Intrinsics for Compare Operations Intrinsics for Fused Multiply Add Operations Intrinsics for GATHER Operations Intrinsics for Logical Shift Operations Intrinsics for Insert/Extract Operations Intrinsics for Masked Load/Store Operations Intrinsics for Miscellaneous Operations Intrinsics for Operations to Manipulate Integer Data at Bit-Granularity Intrinsics for Pack/Unpack Operations Intrinsics for Packed Move with Extend Operations Intrinsics for Permute Operations Intrinsics for Shuffle Operations Intrinsics for Intel® Transactional Synchronization Extensions (Intel® TSX)
Intrinsics for Arithmetic Operations x
<span class='option'>_mm256_abs_epi8/16/32 </span> <span class='option'>_mm256_add_epi8/16/32/64 </span> <span class='option'>_mm256_adds_epi8/16 </span> <span class='option'>_mm256_adds_epu8/16 </span> <span class='option'>_mm256_sub_epi8/16/32/64 </span> <span class='option'>_mm256_subs_epi8/16 </span> <span class='option'>_mm256_subs_epu8/16 </span> <span class='option'>_mm256_avg_epu8/16 </span> <span class='option'>_mm256_hadd_epi16/32 </span> <span class='option'>_mm256_hadds_epi16 </span> <span class='option'>_mm256_hsub_epi16/32 </span> <span class='option'>_mm256_hsubs_epi16 </span> <span class='option'>_mm256_madd_epi16 </span> <span class='option'>_mm256_maddubs_epi16 </span> <span class='option'>_mm256_mul_epi32</span> <span class='option'>_mm256_mul_epu32</span> <span class='option'>_mm256_mulhi_epi16</span> <span class='option'>_mm256_mulhi_epu16 </span> <span class='option'>_mm256_mullo_epi16/32 </span> <span class='option'>_mm256_mulhrs_epi16</span> <span class='option'>_mm256_sign_epi8/16/32</span> <span class='option'>_mm256_mpsadbw_epu8</span> <span class='option'>_mm256_sad_epu8</span>
Intrinsics for Arithmetic Shift Operations x
<span class='option'>_mm256_sra_epi16/32 </span> <span class='option'>_mm256_srai_epi16/32</span> <span class='option'>_mm256_srav_epi32 </span> <span class='option'>_mm_srav_epi32 </span>
Intrinsics for Blend Operations x
<span class='option'>_mm_blend_epi32, _mm256_blend_epi16/32 </span> <span class='option'>_mm256_blendv_epi8 </span>
Intrinsics for Bitwise Operations x
<span class='option'>_mm256_and_si256</span> <span class='option'>_mm256_andnot_si256</span> <span class='option'>_mm256_or_si256</span> <span class='option'>_mm256_xor_si256</span>
Intrinsics for Broadcast Operations x
<span class='option'>_mm_broadcastss_ps, _mm256_broadcastss_ps</span> <span class='option'>_mm256_broadcastsd_pd</span> <span class='option'>_mm_broadcastb_epi8, _mm256_broadcastb_epi8</span> <span class='option'>_mm_broadcastw_epi16, _mm256_broadcastw_epi16</span> <span class='option'>_mm_broadcastd_epi32, _mm256_broadcastd_epi32</span> <span class='option'>_mm_broadcastq_epi64, _mm256_broadcastq_epi64</span> <span class='option'>_mm256_broadcastsi128_si256</span>
Intrinsics for Compare Operations x
<span class='option'>_mm256_cmpeq_epi8/16/32/64</span> <span class='option'>_mm256_cmpgt_epi8/16/32/64</span> <span class='option'>_mm256_max_epi8/16/32</span> <span class='option'>_mm256_max_epu8/16/32</span> <span class='option'>_mm256_min_epi8/16/32</span> <span class='option'>_mm256_min_epu8/16/32</span>
Intrinsics for Fused Multiply Add Operations x
<span class='option'> _mm_fmadd_pd, _mm256_fmadd_pd</span> <span class='option'> _mm_fmadd_ps, _mm256_fmadd_ps</span> <span class='option'> _mm_fmadd_sd </span> <span class='option'> _mm_fmadd_ss </span> <span class='option'> _mm_fmaddsub_pd, _mm256_fmaddsub_pd</span> <span class='option'> _mm_fmaddsub_ps, _mm256_fmaddsub_ps</span> <span class='option'> _mm_fmsub_pd, _mm256_fmsub_pd</span> <span class='option'> _mm_fmsub_ps, _mm256_fmsub_ps</span> <span class='option'> _mm_fmsub_sd </span> <span class='option'> _mm_fmsub_ss </span> <span class='option'> _mm_fmsubadd_pd, _mm256_fmsubadd_pd</span> <span class='option'> _mm_fmsubadd_ps, _mm256_fmsubadd_ps</span> <span class='option'> _mm_fnmadd_pd, _mm256_fnmadd_pd</span> <span class='option'> _mm_fnmadd_ps, _mm256_fnmadd_ps</span> <span class='option'> _mm_fnmadd_sd</span> <span class='option'> _mm_fnmadd_ss</span> <span class='option'> _mm_fnmsub_pd, _mm256_fnmsub_pd</span> <span class='option'> _mm_fnmsub_ps, _mm256_fnmsub_ps</span> <span class='option'> _mm_fnmsub_sd</span> <span class='option'> _mm_fnmsub_ss</span>
Intrinsics for GATHER Operations x
_mm_mask_i32gather_pd, _mm256_mask_i32gather_pd <span class='option'>_mm_i32gather_pd, _mm256_i32gather_pd </span> <span class='option'>_mm_mask_i64gather_pd, _mm256_mask_i64gather_pd </span> <span class='option'>_mm_i64gather_pd, _mm256_i64gather_pd </span> _mm_mask_i32gather_ps, _mm256_mask_i32gather_ps <span class='option'>_mm_i32gather_ps, _mm256_i32gather_ps</span> <span class='option'>_mm_mask_i64gather_ps, _mm256_mask_i64gather_ps</span> <span class='option'>_mm_i64gather_ps, _mm256_i64gather_ps</span> _mm_mask_i32gather_epi32, _mm256_mask_i32gather_epi32 <span class='option'>_mm_i32gather_epi32, _mm256_i32gather_epi32</span> _mm_mask_i32gather_epi64,_mm256_mask_i32gather_epi64 <span class='option'>_mm_i32gather_epi64,_mm256_i32gather_epi64</span> <span class='option'>_mm_mask_i64gather_epi32,_mm256_mask_i64gather_epi32</span> <span class='option'>_mm_i64gather_epi32,_mm256_i64gather_epi32</span> _mm_mask_i64gather_epi64,_mm256_mask_i64gather_epi64 <span class='option'>_mm_i64gather_epi64,_mm256_i64gather_epi64</span>
Intrinsics for Logical Shift Operations x
<span class='option'>_mm256_sll_epi16/32/64 </span> <span class='option'>_mm256_slli_epi16/32/64 </span> <span class='option'>_mm256_sllv_epi32/64 </span> <span class='option'>_mm_sllv_epi32/64 </span> <span class='option'>_mm256_slli_si256 </span> <span class='option'>_mm256_srli_si256</span> <span class='option'>_mm256_srl_epi16/32/64 </span> <span class='option'>_mm256_srli_epi16/32/64 </span> <span class='option'>_mm256_srlv_epi32/64 </span> <span class='option'>_mm_srlv_epi32/64 </span>
Intrinsics for Insert/Extract Operations x
<span class='option'>_mm256_inserti128_si256 </span> <span class='option'>_mm256_extracti128_si256 </span> <span class='option'>_mm256_insert_epi8/16/32/64 </span> <span class='option'>_mm256_extract_epi8/16/32/64 </span>
Intrinsics for Masked Load/Store Operations x
<span class='option'>_mm_maskload_epi32/64, _mm256_maskload_epi32/64</span> <span class='option'>_mm_maskstore_epi32/64, _mm256_maskstore_epi32/64</span>
Intrinsics for Miscellaneous Operations x
<span class='option'>_mm256_alignr_epi8</span> <span class='option'>_mm256_movemask_epi8</span> _mm256_stream_load_si256
Intrinsics for Operations to Manipulate Integer Data at Bit-Granularity x
<span class='option'>_bextr_u32/64 </span> <span class='option'>_blsi_u32/64 </span> <span class='option'>_blsmsk_u32/64 </span> <span class='option'>_blsr_u32/64 </span> <span class='option'>_bzhi_u32/64 </span> <span class='option'>_pext_u32/64 </span> <span class='option'>_pdep_u32/64 </span> <span class='option'>_lzcnt_u32/64 </span> <span class='option'>_tzcnt_u32/64 </span>
Intrinsics for Pack/Unpack Operations x
<span class='option'> _mm256_packs_epi16/32</span> <span class='option'> _mm256_packus_epi16/32</span> <span class='option'> _mm256_unpackhi_epi8/16/32/64</span> <span class='option'> _mm256_unpacklo_epi8/16/32/64</span>
Intrinsics for Packed Move with Extend Operations x
<span class='option'>_mm256_cvtepi8_epi16/32/64</span> <span class='option'>_mm256_cvtepi16_epi32/64</span> <span class='option'>_mm256_cvtepi32_epi64</span> <span class='option'>_mm256_cvtepu8_epi16/32/64</span> <span class='option'>_mm256_cvtepu16_epi32/64</span> <span class='option'>_mm256_cvtepu32_epi64</span>
Intrinsics for Permute Operations x
<span class='option'>_mm256_permutevar8x32_epi32 </span> <span class='option'>_mm256_permutevar8x32_ps </span> <span class='option'>_mm256_permute4x64_epi64 </span> <span class='option'>_mm256_permute4x64_pd </span> <span class='option'>_mm256_permute2x128_si256 </span>
Intrinsics for Shuffle Operations x
<span class='option'>_mm256_shuffle_epi8</span> <span class='option'>_mm256_shuffle_epi32</span> <span class='option'>_mm256_shufflehi_epi16 </span> <span class='option'>_mm256_shufflelo_epi16 </span>
Intrinsics for Intel® Transactional Synchronization Extensions (Intel® TSX) x
Intel® Transactional Synchronization Extensions (Intel® TSX) Overview Intel® Transactional Synchronization Extensions (Intel® TSX) Programming Considerations Intrinsics for Restricted Transactional Memory Operations Intrinsics for Hardware Lock Elision Operations Function Prototype and Macro Definitions
Intrinsics for Restricted Transactional Memory Operations x
Restricted Transactional Memory Overview <span class='option'>_xtest</span> <span class='option'>_xbegin</span> <span class='option'>_xend</span> <span class='option'>_xabort</span>
Intrinsics for Hardware Lock Elision Operations x
Hardware Lock Elision Overview HLE Acquire _InterlockedCompareExchange Functions HLE Acquire _InterlockedExchangeAdd Functions HLE Release _InterlockedCompareExchange Functions HLE Release _InterlockedExchangeAdd Functions HLE Release _Store Functions
Intrinsics for Intel® Advanced Vector Extensions x
Details of Intel® Advanced Vector Extensions Intrinsics Intrinsics for Arithmetic Operations Intrinsics for Bitwise Operations Intrinsics for Blend and Conditional Merge Operations Intrinsics for Compare Operations Intrinsics for Conversion Operations Intrinsics to Determine Minimum and Maximum Values Intrinsics for Load and Store Operations Intrinsics for Miscellaneous Operations Intrinsics for Packed Test Operations Intrinsics for Permute Operations Intrinsics for Shuffle Operations Intrinsics for Unpack and Interleave Operations Support Intrinsics for Vector Typecasting Operations Intrinsics Generating Vectors of Undefined Values
Intrinsics for Arithmetic Operations x
<span class='option'>_mm256_add_pd</span> <span class='option'>_mm256_add_ps</span> <span class='option'>_mm256_addsub_pd</span> <span class='option'>_mm256_addsub_ps</span> <span class='option'> _mm256_hadd_pd</span> <span class='option'>_mm256_hadd_ps</span> <span class='option'>_mm256_sub_pd</span> <span class='option'>_mm256_sub_ps</span> <span class='option'>_mm256_hsub_pd</span> <span class='option'> _mm256_hsub_ps</span> <span class='option'>_mm256_mul_pd</span> <span class='option'>_mm256_mul_ps</span> <span class='option'> _mm256_div_pd</span> <span class='option'> _mm256_div_ps</span> <span class='option'> _mm256_dp_ps</span> <span class='option'>_mm256_sqrt_pd</span> <span class='option'>_mm256_sqrt_ps</span> <span class='option'>_mm256_rsqrt_ps</span> <span class='option'>_mm256_rcp_ps</span>
Intrinsics for Bitwise Operations x
<span class='option'>_mm256_and_pd</span> <span class='option'>_mm256_and_ps</span> <span class='option'>_mm256_andnot_pd</span> <span class='option'>_mm256_andnot_ps</span> <span class='option'>_mm256_or_pd</span> <span class='option'>_mm256_or_ps</span> <span class='option'>_mm256_xor_pd</span> <span class='option'>_mm256_xor_ps</span>
Intrinsics for Blend and Conditional Merge Operations x
<span class='option'>_mm256_blend_pd</span> <span class='option'>_mm256_blend_ps</span> <span class='option'>_mm256_blendv_pd</span> <span class='option'>_mm256_blendv_ps</span>
Intrinsics for Compare Operations x
<span class='option'>_mm_cmp_pd, _mm256_cmp_pd</span> <span class='option'>_mm_cmp_ps, _mm256_cmp_ps</span> <span class='option'> _mm_cmp_sd</span> <span class='option'> _mm_cmp_ss</span>
Intrinsics for Conversion Operations x
<span class='option'> _mm256_cvtepi32_pd</span> <span class='option'> _mm256_cvtepi32_ps</span> <span class='option'> _mm256_cvtpd_epi32</span> <span class='option'> _mm256_cvtps_epi32</span> <span class='option'> _mm256_cvtpd_ps</span> <span class='option'>_mm256_cvtps_pd</span> <span class='option'> _mm256_cvttp_epi32</span> <span class='option'> _mm256_cvttps_epi32</span> _mm256_cvtsi256_si32 _mm256_cvtsd_f64 _mm256_cvtss_f32
Intrinsics to Determine Minimum and Maximum Values x
<span class='option'>_mm256_max_pd</span> <span class='option'>_mm256_max_ps</span> <span class='option'>_mm256_min_pd</span> <span class='option'>_mm256_min_ps</span>
Intrinsics for Load and Store Operations x
<span class='option'>_mm256_broadcast_pd</span> <span class='option'>_mm256_broadcast_ps</span> <span class='option'>_mm256_broadcast_sd</span> <span class='option'>_mm256_broadcast_ss, _mm_broadcast_ss</span> <span class='option'>_mm256_load_pd</span> <span class='option'>_mm256_load_ps</span> <span class='option'>_mm256_load_si256</span> <span class='option'>_mm256_loadu_pd</span> <span class='option'>_mm256_loadu_ps</span> <span class='option'>_mm256_loadu_si256</span> <span class='option'>_mm256_maskload_pd, _mm_maskload_pd</span> <span class='option'>_mm256_maskload_ps, _mm_maskload_ps</span> <span class='option'>_mm256_store_pd</span> <span class='option'>_mm256_store_ps</span> <span class='option'>_mm256_store_si256</span> <span class='option'>_mm256_storeu_pd</span> <span class='option'>_mm256_storeu_ps</span> <span class='option'>_mm256_storeu_si256</span> <span class='option'>_mm256_stream_pd</span> <span class='option'>_mm256_stream_ps</span> <span class='option'>_mm256_stream_si256</span> <span class='option'>_mm256_maskstore_pd, _mm_maskstore_pd</span> <span class='option'>_mm256_maskstore_ps, _mm_maskstore_ps</span>
Intrinsics for Miscellaneous Operations x
<span class='option'> _mm256_extractf128_pd</span> <span class='option'> _mm256_extractf128_ps</span> <span class='option'> _mm256_extractf128_si256</span> <span class='option'>_mm256_insertf128_pd</span> <span class='option'>_mm256_insertf128_ps</span> <span class='option'>_mm256_insertf128_si256</span> <span class='option'>_mm256_lddqu_si256</span> <span class='option'>_mm256_movedup_pd</span> <span class='option'>_mm256_movehdup_ps</span> <span class='option'>_mm256_moveldup_ps</span> <span class='option'>_mm256_movemask_pd</span> <span class='option'>_mm256_movemask_ps</span> <span class='option'>_mm256_round_pd</span> <span class='option'>_mm256_round_ps</span> <span class='option'>_mm256_set_pd</span> <span class='option'>_mm256_set_ps</span> <span class='option'>_mm256_set_epi8/16/32/64x</span> <span class='option'>_mm256_setr_pd</span> <span class='option'>_mm256_setr_ps</span> <span class='option'>_mm256_setr_epi32</span> <span class='option'>_mm256_set1_pd</span> <span class='option'>_mm256_set1_ps</span> <span class='option'>_mm256_set1_epi32</span> <span class='option'>_mm256_setzero_pd</span> <span class='option'>_mm256_setzero_ps</span> <span class='option'>_mm256_setzero_si256</span> <span class='option'>_mm256_zeroall</span> <span class='option'>_mm256_zeroupper</span>
Intrinsics for Packed Test Operations x
<span class='option'>_mm256_testz_si256</span> <span class='option'>_mm256_testc_si256</span> <span class='option'>_mm256_testnzc_si256</span> <span class='option'>_mm256_testz_pd, _mm_testz_pd</span> <span class='option'>_mm256_testz_ps, _mm_testz_ps</span> <span class='option'>_mm256_testc_pd, _mm_testc_pd</span> <span class='option'>_mm256_testc_ps, _mm_testc_ps</span> <span class='option'>_mm256_testnzc_pd, _mm_testnzc_pd</span> <span class='option'>_mm256_testnzc_ps, _mm_testnzc_ps</span>
Intrinsics for Permute Operations x
<span class='option'>_mm256_permute_pd, _mm_permute_pd</span> <span class='option'>_mm256_permute_ps, _mm_permute_ps</span> <span class='option'>_mm256_permutevar_pd, _mm_permutevar_pd</span> <span class='option'>_mm_permutevar_ps, _mm256_permutevar_ps</span> <span class='option'>_mm256_permute2f128_pd</span> <span class='option'>_mm256_permute2f128_ps</span> <span class='option'>_mm256_permute2f128_si256</span>
Intrinsics for Shuffle Operations x
<span class='option'>_mm256_shuffle_pd</span> <span class='option'>_mm256_shuffle_ps</span>
Intrinsics for Unpack and Interleave Operations x
<span class='option'>_mm256_unpackhi_pd</span> <span class='option'>_mm256_unpackhi_ps</span> <span class='option'>_mm256_unpacklo_pd</span> <span class='option'>_mm256_unpacklo_ps</span>
Support Intrinsics for Vector Typecasting Operations x
<span class='option'>_mm256_castpd_ps</span> <span class='option'> _mm256_castps_pd</span> <span class='option'>_mm256_castpd_si256</span> <span class='option'> _mm256_castps_si256</span> <span class='option'> _mm256_castsi256_pd</span> <span class='option'> _mm256_castsi256_ps</span> <span class='option'>_mm256_castpd128_pd256</span> <span class='option'>_mm256_castpd256_pd128</span> <span class='option'> _mm256_castps128_ps256</span> <span class='option'> _mm256_castps256_ps128</span> <span class='option'> _mm256_castsi128_si256</span> <span class='option'> _mm256_castsi256_si128</span>
Intrinsics Generating Vectors of Undefined Values x
_mm256_undefined_ps() _mm256_undefined_pd() _mm256_undefined_si256
Intrinsics for Intel® Streaming SIMD Extensions 4 (Intel® SSE4) x
Efficient Accelerated String and Text Processing Vectorizing Compiler and Media Accelerators
Efficient Accelerated String and Text Processing x
Overview: Efficient Accelerated String and Text Processing Packed Compare Intrinsics Application Targeted Accelerators Intrinsics
Vectorizing Compiler and Media Accelerators x
Overview: Vectorizing Compiler and Media Accelerators Packed Blending Intrinsics Floating Point Dot Product Intrinsics Packed Format Conversion Intrinsics Packed Integer Min/Max Intrinsics Floating Point Rounding Intrinsics DWORD Multiply Intrinsics Register Insertion/Extraction Intrinsics Test Intrinsics Packed DWORD to Unsigned WORD Intrinsic Packed Compare for Equal Intrinsic Cacheability Support Intrinsic
Intrinsics for Intel® Supplemental Streaming SIMD Extensions 3 (SSSE3) x
Addition Intrinsics Subtraction Intrinsics Multiplication Intrinsics Absolute Value Intrinsics Shuffle Intrinsics Concatenate Intrinsics Negation Intrinsics
Intrinsics for Intel® Streaming SIMD Extensions 3 (Intel® SSE3) x
Integer Vector Intrinsic Single-precision Floating-point Vector Intrinsics Double-precision Floating-point Vector Intrinsics Miscellaneous Intrinsics
Intrinsics for Intel® Streaming SIMD Extensions 2 (Intel® SSE2) x
Macro Functions Floating-point Intrinsics Integer Intrinsics Miscellaneous Functions and Intrinsics
Floating-point Intrinsics x
Arithmetic Intrinsics Logical Intrinsics Compare Intrinsics Conversion Intrinsics Load Intrinsics Set Intrinsics Store Intrinsics
Integer Intrinsics x
Arithmetic Intrinsics Logical Intrinsics Shift Intrinsics Compare Intrinsics Conversion Intrinsics Move Intrinsics Load Intrinsics Set Intrinsics Store Intrinsics
Miscellaneous Functions and Intrinsics x
Cacheability Support Intrinsics Miscellaneous Intrinsics Casting Support Intrinsics Pause Intrinsic Macro Function for Shuffle Intrinsics Returning Vectors of Undefined Values
Intrinsics for Intel® Streaming SIMD Extensions (Intel® SSE) x
Details about Intel® Streaming SIMD Extensions Intrinsics Writing Programs with Intel® Streaming SIMD Extensions (Intel® SSE) Intrinsics Arithmetic Intrinsics Logical Intrinsics Compare Intrinsics Conversion Intrinsics Load Intrinsics Set Intrinsics Store Intrinsics Cacheability Support Intrinsics Integer Intrinsics Intrinsics to Read and Write Registers Miscellaneous Intrinsics Macro Functions
Macro Functions x
Macro Function for Shuffle Operations Macro Functions to Read and Write Control Registers Macro Function for Matrix Transposition
Intrinsics for MMX™ Technology x
Details about MMX™ Technology Intrinsics The EMMS Instruction: Why You Need It EMMS Usage Guidelines General Support Intrinsics (MMX™ technology) Packed Arithmetic Intrinsics (MMX™ technology) Shift Intrinsics (MMX™ technology) Logical Intrinsics (MMX™ technology) Compare Intrinsics (MMX™ technology) Set Intrinsics (MMX™ technology)
Intrinsics for Advanced Encryption Standard Implementation x
Intrinsics for Carry-less Multiplication Instruction and Advanced Encryption Standard Instructions
Intrinsics for Converting Half Floats x
Details About Intrinsics for Half Floats
Intrinsics for Short Vector Math Library Operations (SVML) x
Intrinsics for Division Operations (512-bit) Intrinsics for Division Operations Intrinsics for Error Function Operations (512-bit) Intrinsics for Error Function Operations Intrinsics for Exponential Operations (512-bit) Intrinsics for Exponential Operations Intrinsics for Logarithmic Operations (512-bit) Intrinsics for Logarithmic Operations Intrinsics for Reciprocal Operations (512-bit) Intrinsics for Root Function Operations (512-bit) Intrinsics for Rounding Operations (512-bit) Intrinsics for Square Root and Cube Root Operations Intrinsics for Trigonometric Operations (512-bit) Intrinsics for Trigonometric Operations
Intrinsics for Division Operations x
_mm_div_epi8/ _mm256_div_epi8 _mm_div_epi16/ _mm256_div_epi16 _mm_div_epi32/ _mm256_div_epi32 _mm_div_epi64/ _mm256_div_epi64 _mm_div_epu8/ _mm256_div_epu8 _mm_div_epu16/ _mm256_div_epu16 _mm_div_epu32/ _mm256_div_epu32 _mm_div_epu64/ _mm256_div_epu64 _mm_rem_epi8/ _mm256_rem_epi8 _mm_rem_epi16/ _mm256_rem_epi16 _mm_rem_epi32/ _mm256_rem_epi32 _mm_rem_epi64/ _mm256_rem_epi64 _mm_rem_epu8/ _mm256_rem_epu8 _mm_rem_epu16/ _mm256_rem_epu16 _mm_rem_epu32/ _mm256_rem_epu32 _mm_rem_epu64/ _mm256_rem_epu64
Intrinsics for Error Function Operations x
<span class='option'> _mm_cdfnorminv_pd</span>, <span class='option'>_mm256_cdfnorminv_pd</span> <span class='option'> _mm_cdfnorminv_ps</span>, <span class='option'>_mm256_cdfnorminv_ps</span> <span class='option'> _mm_erf_pd</span>,<span class='option'> _mm256_erf_pd</span> <span class='option'> _mm_erf_ps</span>, <span class='option'>_mm256_erf_ps</span> <span class='option'>_mm_erfc_pd</span>, <span class='option'>_mm256_erfc_pd</span> <span class='option'> _mm_erfc_ps</span>, <span class='option'>_mm256_erfc_ps</span> <span class='option'> _mm_erfinv_pd</span>,<span class='option'> _mm256_erfinv_pd</span> <span class='option'> _mm_erfinv_ps</span>, <span class='option'>_mm256_erfinv_ps</span>
Intrinsics for Exponential Operations x
<span class='option'> _mm_exp2_pd</span>, <span class='option'>_mm256_exp2_pd</span> <span class='option'> _mm_exp2_ps</span>, <span class='option'>_mm256_exp2_ps</span> <span class='option'> _mm_exp_pd</span>, <span class='option'>_mm256_exp_pd</span> <span class='option'> _mm_exp_ps</span>, <span class='option'>_mm256_exp_ps</span> <span class='option'> _mm_exp10_pd</span>, <span class='option'>_mm256_exp10_pd</span> <span class='option'> _mm_exp10_ps</span>, <span class='option'>_mm256_exp10_ps</span> <span class='option'> _mm_expm1_pd</span>, <span class='option'>_mm256_expm1_pd</span> <span class='option'> _mm_expm1_ps</span>, <span class='option'>_mm256_expm1_ps</span> <span class='option'> _mm_cexp_ps</span>, <span class='option'>_mm256_cexp_ps</span> <span class='option'>_mm_pow_pd</span>, <span class='option'>_mm256_pow_pd</span> <span class='option'> _mm_pow_ps</span>, <span class='option'>_mm256_pow_ps</span> <span class='option'> _mm_hypot_pd</span>, <span class='option'>_mm256_hypot_pd</span> <span class='option'> _mm_hypot_ps</span>, <span class='option'>_mm256_hypot_ps</span>
Intrinsics for Logarithmic Operations x
<span class='option'> _mm_log2_pd</span>, <span class='option'>_mm256_log2_pd</span> <span class='option'>_mm_log2_ps</span>, <span class='option'>_mm256_log2_ps</span> <span class='option'>_mm_log10_pd</span>, <span class='option'>_mm256_log10_pd</span> <span class='option'>_mm_log10_ps</span>, <span class='option'>_mm256_log10_ps</span> <span class='option'> _mm_log_pd</span>, <span class='option'>_mm256_log_pd</span> <span class='option'>_mm_log_ps</span>, <span class='option'>_mm256_log_ps</span> <span class='option'> _mm_logb_pd</span>, <span class='option'>_mm256_logb_pd</span> <span class='option'> _mm_logb_ps</span>, <span class='option'>_mm256_logb_ps</span> <span class='option'> _mm_log1p_pd</span>, <span class='option'>_mm256_log1p_pd</span> <span class='option'> _mm_log1p_ps</span>, <span class='option'>_mm256_log1p_ps</span> <span class='option'>_mm_clog_ps</span>, <span class='option'>_mm256_clog_ps</span>
Intrinsics for Square Root and Cube Root Operations x
<span class='option'> _mm_sqrt_pd</span>, <span class='option'>_mm256_sqrt_pd</span> <span class='option'>_mm_sqrt_ps</span>, <span class='option'>_mm256_sqrt_ps</span> <span class='option'> _mm_invsqrt_pd</span>, <span class='option'>_mm256_invsqrt_pd</span> <span class='option'> _mm_invsqrt_ps</span>, <span class='option'>_mm256_invsqrt_ps</span> <span class='option'>_mm_cbrt_pd</span>, <span class='option'>_mm256_cbrt_pd</span> <span class='option'>_mm_cbrt_ps</span>, <span class='option'>_mm256_cbrt_ps</span> <span class='option'>_mm_invcbrt_pd</span>, <span class='option'>_mm256_invcbrt_pd</span> <span class='option'>_mm_invcbrt_ps</span>, <span class='option'>_mm256_invcbrt_ps</span> <span class='option'>_mm_csqrt_ps</span>, <span class='option'>_mm256_csqrt_ps</span>
Intrinsics for Trigonometric Operations x
<span class='option'> _mm_acos_pd</span>, <span class='option'>_mm256_acos_pd</span> <span class='option'>_mm_acos_ps</span>, <span class='option'>_mm256_acos_ps</span> <span class='option'> _mm_acosh_pd</span>, <span class='option'>_mm256_acosh_pd</span> <span class='option'> _mm_acosh_ps</span>, <span class='option'>_mm256_acosh_ps</span> <span class='option'> _mm_asin_pd</span>, <span class='option'>_mm256_asin_pd</span> <span class='option'>_mm_asin_ps</span>, <span class='option'>_mm256_asin_ps</span> <span class='option'> _mm_asinh_pd</span>, <span class='option'>_mm256_asinh_pd</span> <span class='option'> _mm_asinh_ps</span>, <span class='option'>_mm256_asinh_ps</span> <span class='option'>_mm_atan_pd</span>, <span class='option'>_mm256_atan_pd</span> <span class='option'> _mm_atan_ps</span>, <span class='option'>_mm256_atan_ps</span> <span class='option'> _mm_atan2_pd</span>, <span class='option'>_mm256_atan2_pd</span> <span class='option'>_mm_atan2_ps</span>, <span class='option'>_mm256_atan2_ps</span> <span class='option'>_mm_atanh_pd</span>, <span class='option'>_mm256_atanh_pd</span> <span class='option'> _mm_atanh_ps</span>, <span class='option'>_mm256_atanh_ps</span> <span class='option'> _mm_cos_pd</span>, <span class='option'>_mm256_cos_pd</span> <span class='option'> _mm_cos_ps</span>, <span class='option'>_mm256_cos_ps</span> <span class='option'> _mm_cosd_pd</span>, <span class='option'>_mm256_cosd_pd</span> <span class='option'> _mm_cosd_ps</span>, <span class='option'>_mm256_cosd_ps</span> <span class='option'>_mm_cosh_pd</span>, <span class='option'>_mm256_cosh_pd</span> <span class='option'> _mm_cosh_ps</span>, <span class='option'>_mm256_cosh_ps</span> <span class='option'>_mm_sin_pd</span>, <span class='option'>_mm256_sin_pd</span> <span class='option'>_mm_sin_ps</span>, <span class='option'>_mm256_sin_ps</span> <span class='option'>_mm_sind_pd</span>, <span class='option'>_mm256_sind_pd</span> <span class='option'>_mm_sind_ps</span>, <span class='option'>_mm256_sind_ps</span> <span class='option'>_mm_sinh_pd</span>, <span class='option'>_mm256_sinh_pd</span> <span class='option'>_mm_sinh_ps</span>, <span class='option'>_mm256_sinh_ps</span> <span class='option'>_mm_tan_pd</span>, <span class='option'>_mm256_tan_pd</span> <span class='option'> _mm_tan_ps</span>, <span class='option'>_mm256_tan_ps</span> <span class='option'>_mm_tand_pd</span>, <span class='option'>_mm256_tand_pd</span> <span class='option'> _mm_tand_ps</span>, <span class='option'>_mm256_tand_ps</span> <span class='option'>_mm_tanh_pd</span>, <span class='option'>_mm256_tanh_pd</span> <span class='option'>_mm_tanh_ps</span>, <span class='option'>_mm256_tanh_ps</span> <span class='option'>_mm_sincos_pd</span>, <span class='option'>_mm256_sincos_pd</span> <span class='option'>_mm_sincos_ps</span>, <span class='option'>_mm256_sincos_ps</span>
Libraries x
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Intel® C++ Compiler Classic Developer Guide and Reference

Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) BF16 Instructions

The prototypes for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) BF16 instruction intrinsics are located in the zmmintrin.h header file.

To use these intrinsics, include the immintrin.h file as follows: 

#include <immintrin.h>
variable definition
a a source vector element
b a second source vector element
k mask used as a selector; depending on the intrinsic, it may be a writemask or a zeromask

_mm_cvtne2ps_pbh

__m128bh _mm_cvtne2ps_pbh (__m128 a, __m128 b)

Instructions: vcvtne2ps2bf16 xmm, xmm, xmm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in two vectors a and b to packed BF16 (16-bit) floating-point elements, and stores the results in a single vector dst.



_mm_mask_cvtne2ps_pbh

__m128bh _mm_mask_cvtne2ps_pbh (__m128bh src, __mmask8 k, __m128 a, __m128 b)

Instructions: vcvtne2ps2bf16 xmm {k}, xmm, xmm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in two vectors a and b to packed BF16 (16-bit) floating-point elements, and stores the results in a single vector dst using writemask k. Elements are copied from src when the corresponding mask bit is not set.



_mm_maskz_cvtne2ps_pbh

__m128bh _mm_maskz_cvtne2ps_pbh (__mmask8 k, __m128 a, __m128 b)

Instructions: vcvtne2ps2bf16 xmm {k}{z}, xmm, xmm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in two vectors a and b to packed BF16 (16-bit) floating-point elements, and stores the results in a single vector dst using zeromask k. Elements are zeroed out when the corresponding mask bit is not set.



_mm256_cvtne2ps_pbh

__m256bh _mm256_cvtne2ps_pbh (__m256 a, __m256 b)

Instructions: vcvtne2ps2bf16 ymm, ymm, ymm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in two vectors a and b to packed BF16 (16-bit) floating-point elements, and stores the results in a single vector dst.



_mm256_mask_cvtne2ps_pbh

__m256bh _mm256_mask_cvtne2ps_pbh (__m256bh src, __mmask16 k, __m256 a, __m256 b)

Instructions: vcvtne2ps2bf16 ymm {k}, ymm, ymm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in two vectors a and b to packed BF16 (16-bit) floating-point elements, and stores the results in a single vector dst using writemask k. Elements are copied from src when the corresponding mask bit is not set.



_mm256_maskz_cvtne2ps_pbh

__m256bh _mm256_maskz_cvtne2ps_pbh (__mmask16 k, __m256 a, __m256 b)

Instructions: vcvtne2ps2bf16 ymm {k}{z}, ymm, ymm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in two vectors a and b to packed BF16 (16-bit) floating-point elements, and store the results in single vector dst using zeromask k. Elements are zeroed out when the corresponding mask bit is not set.



_mm512_cvtne2ps_pbh

__m512bh _mm512_cvtne2ps_pbh (__m512 a, __m512 b)

Instructions: vcvtne2ps2bf16 zmm, zmm, zmm

CPUID Flags: AVX512_BF16 + AVX512F

Converts packed single-precision (32-bit) floating-point elements in two vectors a and b to packed BF16 (16-bit) floating-point elements, and stores the results in a single vector dst.



_mm512_mask_cvtne2ps_pbh

__m512bh _mm512_mask_cvtne2ps_pbh (__m512bh src, __mmask32 k, __m512 a, __m512 b)

Instructions: vcvtne2ps2bf16 zmm {k}, zmm, zmm

CPUID Flags: AVX512_BF16 + AVX512F

Converts packed single-precision (32-bit) floating-point elements in two vectors a and b to packed BF16 (16-bit) floating-point elements, and stores the results in a single vector dst using writemask k. Elements are copied from src when the corresponding mask bit is not set.



_mm512_maskz_cvtne2ps_pbh

__m512bh _mm512_maskz_cvtne2ps_pbh (__mmask32 k, __m512 a, __m512 b)

Instructions: vcvtne2ps2bf16 zmm {k}{z}, zmm, zmm

CPUID Flags: AVX512_BF16 + AVX512F

Converts packed single-precision (32-bit) floating-point elements in two vectors a and b to packed BF16 (16-bit) floating-point elements, and stores the results in a single vector dst using zeromask k. Elements are zeroed out when the corresponding mask bit is not set.



_mm_cvtneps_pbh

__m128bh _mm_cvtneps_pbh (__m128 a)

Instructions: vcvtneps2bf16 xmm, xmm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and stores the results in dst.



_mm_mask_cvtneps_pbh

__m128bh _mm_mask_cvtneps_pbh (__m128bh src, __mmask8 k, __m128 a)

Instructions: vcvtneps2bf16 xmm {k}, xmm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and stores the results in dst using writemask k. Elements are copied from src when the corresponding mask bit is not set.



_mm_maskz_cvtneps_pbh

__m128bh _mm_maskz_cvtneps_pbh (__mmask8 k, __m128 a)

Instructions: vcvtneps2bf16 xmm {k}{z}, xmm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and stores the results in dst using zeromask k. Elements are zeroed out when the corresponding mask bit is not set.



_mm256_cvtneps_pbh

__m128bh _mm256_cvtneps_pbh (__m256 a)

Instructions: vcvtneps2bf16 xmm, ymm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and stores the results in dst.



_mm256_mask_cvtneps_pbh

__m128bh _mm256_mask_cvtneps_pbh (__m128bh src, __mmask8 k, __m256 a)

Instructions: vcvtneps2bf16 xmm {k}, ymm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and stores the results in dst using writemask k. Elements are copied from src when the corresponding mask bit is not set.



_mm256_maskz_cvtneps_pbh

__m128bh _mm256_maskz_cvtneps_pbh (__mmask8 k, __m256 a)

Instructions: vcvtneps2bf16 xmm {k}{z}, ymm

CPUID Flags: AVX512_BF16 + AVX512VL

Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and stores the results in dst using zeromask k. Elements are zeroed out when the corresponding mask bit is not set.



_mm512_cvtneps_pbh

__m256bh _mm512_cvtneps_pbh (__m512 a)

Instructions: vcvtneps2bf16 ymm, zmm

CPUID Flags: AVX512_BF16 + AVX512F

Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and stores the results in dst.



_mm512_mask_cvtneps_pbh

__m256bh _mm512_mask_cvtneps_pbh (__m256bh src, __mmask16 k, __m512 a)

Instructions: vcvtneps2bf16 ymm {k}, zmm

CPUID Flags: AVX512_BF16 + AVX512F

Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and stores the results in dst using writemask k. Elements are copied from src when the corresponding mask bit is not set.



_mm512_maskz_cvtneps_pbh

__m256bh _mm512_maskz_cvtneps_pbh (__mmask16 k, __m512 a)

Instructions: vcvtneps2bf16 ymm {k}{z}, zmm

CPUID Flags: AVX512_BF16 + AVX512F

Converts packed single-precision (32-bit) floating-point elements in a to packed BF16 (16-bit) floating-point elements, and stores the results in dst using zeromask k. Elements are zeroed out when the corresponding mask bit is not set.



_mm_dpbf16_ps

__m128 _mm_dpbf16_ps (__m128 src, __m128bh a, __m128bh b)

Instructions: vdpbf16ps xmm, xmm, xmm

CPUID Flags: AVX512_BF16 + AVX512VL

Computes the dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and stores the results in dst.



_mm_mask_dpbf16_ps

__m128 _mm_mask_dpbf16_ps (__m128 src, __mmask8 k, __m128bh a, __m128bh b)

Instructions: vdpbf16ps xmm {k}, xmm, xmm

CPUID Flags: AVX512_BF16 + AVX512VL

Computes the dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and stores the results in dst using writemask k. Elements are copied from src when the corresponding mask bit is not set.



_mm_maskz_dpbf16_ps

__m128 _mm_maskz_dpbf16_ps (__mmask8 k, __m128 src, __m128bh a, __m128bh b)

Instructions: vdpbf16ps xmm {k}{z}, xmm, xmm

CPUID Flags: AVX512_BF16 + AVX512VL

Computes the dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and stores the results in dst using zeromask k. Elements are zeroed out when the corresponding mask bit is not set).



_mm256_dpbf16_ps

__m256 _mm256_dpbf16_ps (__m256 src, __m256bh a, __m256bh b)

Instructions: vdpbf16ps ymm, ymm, ymm

CPUID Flags: AVX512_BF16 + AVX512VL

Computes the dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and stores the results in dst.



_mm256_mask_dpbf16_ps

__m256 _mm256_mask_dpbf16_ps (__m256 src, __mmask8 k, __m256bh a, __m256bh b)

Instructions: vdpbf16ps ymm {k}, ymm, ymm

CPUID Flags: AVX512_BF16 + AVX512VL

Computes the dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and stores the results in dst using writemask k. Elements are copied from src when the corresponding mask bit is not set.



_mm256_maskz_dpbf16_ps

__m256 _mm256_maskz_dpbf16_ps (__mmask8 k, __m256 src, __m256bh a, __m256bh b)

Instructions: vdpbf16ps ymm {k}{z}, ymm, ymm

CPUID Flags: AVX512_BF16 + AVX512VL

Computes the dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and stores the results in dst using zeromask k. Elements are zeroed out when the corresponding mask bit is not set).



_mm512_dpbf16_ps

__m512 _mm512_dpbf16_ps (__m512 src, __m512bh a, __m512bh b)

Instructions: vdpbf16ps zmm, zmm, zmm

CPUID Flags: AVX512_BF16 + AVX512F

Computes the dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and stores the results in dst.



_mm512_mask_dpbf16_ps

__m512 _mm512_mask_dpbf16_ps (__m512 src, __mmask16 k, __m512bh a, __m512bh b)

Instructions: vdpbf16ps zmm {k}, zmm, zmm

CPUID Flags: AVX512_BF16 + AVX512F

Computes the dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and stores the results in dst using writemask k. Elements are copied from src when the corresponding mask bit is not set.



_mm512_maskz_dpbf16_ps

__m512 _mm512_maskz_dpbf16_ps (__mmask16 k, __m512 src, __m512bh a, __m512bh b)

Instructions: vdpbf16ps zmm {k}{z}, zmm, zmm

CPUID Flags: AVX512_BF16 + AVX512F

Computes the dot-product of BF16 (16-bit) floating-point pairs in a and b, accumulating the intermediate single-precision (32-bit) floating-point elements with elements in src, and stores the results in dst using zeromask k. Elements are zeroed out when the corresponding mask bit is not set.



Parent topic: Intrinsics
Level Two Title