Intel® Advisor User Guide

Download PDF
ID 766448
Date 3/31/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
Intel® Advisor User Guide
Intel® Advisor User Guide x
Introduction Install and Launch Intel® Advisor Set Up Project Analyze Vectorization Perspective Analyze CPU Roofline Model Threading Designs Model Offloading to a GPU Analyze GPU Roofline Design and Analyze Flow Graphs Minimize Analysis Overhead Analyze MPI Applications Manage Results Command Line Interface Troubleshooting Reference Appendix Notices and Disclaimers
Introduction x
Design and Optimization Methodology Tutorials and Samples Get Help and Support
Install and Launch Intel® Advisor x
Install Intel® Advisor Set Up Environment Variables Set Up System to Analyze GPU Kernels Set Up Environment to Offload SYCL, OpenMP* target, and OpenCL™ Applications to CPU Launch Intel® Advisor GUI Navigation Quick Start
Set Up Project x
Configure Target Application Build Target Application Create Project
Configure Target Application x
Limit the Number of Threads Used by Parallel Frameworks Choose a Small, Representative Data Set
Create Project x
Configure Project Configure Binary/Symbol Search Directories Configure Source Search Directory Binary/Symbol Search and Source Search Locations
Analyze Vectorization Perspective x
Run Vectorization and Code Insights Perspective from GUI Run Vectorization and Code Insights Perspective from Command Line Explore Vectorization and Code Insights Results
Run Vectorization and Code Insights Perspective from GUI x
Vectorization Accuracy Presets Customize Vectorization and Code Insights Perspective
Run Vectorization and Code Insights Perspective from Command Line x
Vectorization Accuracy Levels in Command Line
Explore Vectorization and Code Insights Results x
Vectorization Report Overview Examine Not-Vectorized and Under-Vectorized Loops Analyze Loop Call Count Investigate Memory Usage and Traffic Find Data Dependencies
Analyze CPU Roofline x
Run CPU / Memory Roofline Insights Perspective from GUI Run CPU / Memory Roofline Insights Perspective from Command Line Explore CPU/Memory Roofline Results
Run CPU / Memory Roofline Insights Perspective from GUI x
CPU Roofline Accuracy Presets Customize CPU / Memory Roofline Insights Perspective
Run CPU / Memory Roofline Insights Perspective from Command Line x
CPU Roofline Accuracy Levels in Command Line
Explore CPU/Memory Roofline Results x
CPU Roofline Report Overview Examine Bottlenecks on CPU Roofline Chart Examine Relationships Between Memory Levels Accuracy Level Enabled Analyses Result Interpretation Memory-Level Roofline Roofline with Callstacks See Also Compare CPU Roofline Results
Model Threading Designs x
Run Threading Perspective from GUI Run Threading Perspective from Command Line Annotate Code for Deeper Analysis Explore Threading Results Model Threading Parallelism Check for Dependencies Issues Add Parallelism to Your Program
Run Threading Perspective from GUI x
Customize Threading Perspective
Run Threading Perspective from Command Line x
Threading Accuracy Levels in Command Line
Annotate Code for Deeper Analysis x
Annotate Code to Model Parallelism Annotations Annotation Report
Annotate Code to Model Parallelism x
Before Annotating Code for Deeper Analysis Use Amdahl's Law and Measure the Program Task Organization and Annotations Annotate Parallel Sites and Tasks Task Patterns Choose the Tasks Use Partially Parallel Programs with Intel® Advisor
Task Patterns x
Multiple Parallel Sites Data and Task Parallelism Mix and Match Tasks
Choose the Tasks x
Task Interactions and Suitability How Big Should a Task Be?
Annotations x
Annotation Types Annotation Definitions Files Add Annotations into Your Source Code Tips for Annotation Use with C/C++ Programs
Annotation Types x
Annotation Types Summary Annotation General Characteristics Site and Task Annotations for Simple Loops With One Task Site and Task Annotations for Parallel Sites with Multiple Tasks Lock Annotations Pause Collection and Resume Collection Annotations Special-purpose Annotations
Annotation Definitions Files x
Reference the Annotations Definitions Directory Add a Copy of the C/C++ Annotation Definition File to Your Visual Studio* Project Include the Annotations Header File in C/C++ Sources
Add Annotations into Your Source Code x
Insert Annotations Using the Annotation Wizard Copy Annotations and Build Settings Using the Annotation Assistant Pane Insert Annotations in the Visual Studio* Code Editor Insert Annotations in a Text Editor
Insert Annotations Using the Annotation Wizard x
Annotation Wizard - Page 1 Annotation Wizard - Page 2 Annotation Wizard - Page 3
Tips for Annotation Use with C/C++ Programs x
Control the Expansion of advisor-annotate.h Handle Compilation Issues that Appear After Adding advisor-annotate.h advisor-annotate.h and libittnotify.dll
Annotation Report x
Annotation Report, Clear Description of Storage Row Annotation Report, Disable Observations in Region Row Annotation Report, Pause Collection Row Annotation Report, Inductive Expression Row Annotation Report, Lock Row Annotation Report, Observe Uses Row Annotation Report, Reduction Row Annotation Report, Re-enable Observations at End of Region Row Annotation Report, Resume Collection Row Annotation Report, Site Row Annotation Report, Task Row Annotation Report, User Memory Allocator Use Row Annotation Report, User Memory Deallocator Use Row
Model Threading Parallelism x
Suitability Report Overview Choose Modeling Parameters in the Suitability Report Fix Annotation-related Errors Detected by the Suitability Tool Advanced Modeling Options Reduce Parallel Overhead, Lock Contention, and Enable Chunking
Reduce Parallel Overhead, Lock Contention, and Enable Chunking x
Reduce Site Overhead Reduce Task Overhead Reduce Lock Overhead Reduce Lock Contention Enable Task Chunking
Check for Dependencies Issues x
Code Locations Pane Filter Pane (Dependencies Report) Problems and Messages Pane Dependencies Source Window
Dependencies Source Window x
Code Locations Pane (Dependencies Source Window) Focus Code Location Pane Focus Code Location Call Stack Pane Related Code Locations Pane Related Code Location Call Stack Pane Relationship Diagram Pane
Add Parallelism to Your Program x
Before You Add Parallelism: Choose a Parallel Framework Add the Parallel Framework to Your Build Environment Annotation Report Replace Annotations with Intel® oneAPI Threading Building Blocks (oneTBB) Code Replace Annotations with OpenMP* Code Next Steps for the Parallel Program
Before You Add Parallelism: Choose a Parallel Framework x
Parallel Frameworks Intel® oneAPI Threading Building Blocks (oneTBB) OpenMP* Microsoft Task Parallel Library* (TPL) Other Parallel Frameworks
Add the Parallel Framework to Your Build Environment x
Enable Intel® oneAPI Threading Building Blocks (oneTBB) in your Build Environment Define the TBBROOT Environment Variable Enable C++11 Lambda Expression Support with Intel® oneAPI Threading Building Blocks (oneTBB) Enable OpenMP* in your Build Environment
Annotation Report x
Annotation Report Overview Locate Annotations with the Annotation Report
Replace Annotations with Intel® oneAPI Threading Building Blocks (oneTBB) Code x
Intel® oneAPI Threading Building Blocks (oneTBB) Mutexes Intel® oneAPI Threading Building Blocks (oneTBB) Simple Mutex - Example Test the Intel® oneAPI Threading Building Blocks (oneTBB) Synchronization Code Parallelize Functions - Intel® oneAPI Threading Building Blocks (oneTBB) Tasks Parallelize Data - Intel® oneAPI Threading Building Blocks (oneTBB) Counted Loops Parallelize Data - Intel® oneAPI Threading Building Blocks (oneTBB) Loops with Complex Iteration Control
Replace Annotations with OpenMP* Code x
Add OpenMP Code to Synchronize the Shared Resources OpenMP Critical Sections Basic OpenMP Atomic Operations Advanced OpenMP Atomic Operations OpenMP Reduction Operations OpenMP Locks Test the OpenMP Synchronization Code Parallelize Functions - OpenMP Tasks Parallelize Data - OpenMP Counted Loops Parallelize Data - OpenMP Loops with Complex Iteration Control
Next Steps for the Parallel Program x
Use Intel® Inspector and Intel® VTune™ Profiler Debug Parallel Programs
Model Offloading to a GPU x
Run Offload Modeling Perspective from GUI Run Offload Modeling Perspective from Command Line Explore Offload Modeling Results Advanced Modeling Configuration
Run Offload Modeling Perspective from GUI x
Offload Modeling Accuracy Presets Customize Offload Modeling Perspective
Run Offload Modeling Perspective from Command Line x
Offload Modeling Accuracy Levels in Command Line Run GPU-to-GPU Performance Modeling from Command Line
Explore Offload Modeling Results x
Offload Modeling Report Overview Examine Regions Recommended for Offloading Examine Data Transfers for Modeled Regions Check for Dependency Issues Explore Performance Gain from GPU-to-GPU Modeling Investigate Non-Offloaded Code Regions
Advanced Modeling Configuration x
Model Application Performance on a Custom Target GPU Device Check How Assumed Dependencies Affect Modeling Manage Invocation Taxes Enforce Offloading for Specific Loops
Analyze GPU Roofline x
Run GPU Roofline Insights Perspective from GUI Run GPU Roofline Insights Perspective from Command Line Explore GPU Roofline Results
Run GPU Roofline Insights Perspective from GUI x
GPU Roofline Accuracy Presets Customize GPU Roofline Insights Perspective
Run GPU Roofline Insights Perspective from Command Line x
GPU Roofline Accuracy Levels in Command Line
Explore GPU Roofline Results x
Examine GPU Roofline Summary Examine Bottlenecks on GPU Roofline Chart Examine Kernel Details Compare GPU Roofline Results
Design and Analyze Flow Graphs x
Where to Find the Flow Graph Analyzer Launching the Flow Graph Analyzer Flow Graph Analyzer GUI Overview Flow Graph Analyzer Workflows Designer Workflow Generating C++ Stubs Preferences Scalability Analysis Collecting Traces from Applications Nested Parallelism in Flow Graph Analyzer Analyzer Workflow Experimental Support for OpenMP* Applications Sample Trace Files Additional Resources
Flow Graph Analyzer GUI Overview x
Menus Toolbars Tabs Main Canvas Charts
Designer Workflow x
Adding Nodes, Edges, and Ports Modifying Node Properties Viewing Edge Properties Validating a Graph Saving a Graph to a File
Scalability Analysis x
Activating the Graph Scalability Analysis Prerequisites Running the Scalability Analysis Exploring the Parallelism in a Concurrent Node Showing Non-Parallel Nature of a Serial Node Explore Parallelism Provided by the Topology of a Graph Understanding Analysis Color Codes
Scalability Analysis Prerequisites x
Setting Concurrency Specification Setting Data Count Setting Node Weight
Collecting Traces from Applications x
Building an Application for Trace Collection Collecting Trace Files
Building an Application for Trace Collection x
Building an Application on Windows* OS Building an Application on Linux* OS Building an Application on macOS*
Collecting Trace Files x
Collect Traces In the Flow Graph Analyzer GUI Collect Traces Outside the Flow Graph Analyzer GUI
Collect Traces Outside the Flow Graph Analyzer GUI x
Collecting Trace Files with fgtrun Script Collecting Trace Files without fgtrun Script
Analyzer Workflow x
Find Time Regions of Low Concurrency and Their Cause Finding a Critical Path Finding Tasks with Small Durations Reduce Scheduler Overhead using Lightweight Policy Identifying Tasks that Operate on Common Input Support for SYCL
Support for SYCL x
Collect SYCL Application Traces Examine a SYCL Application Graph Find Issues Using Static Rule-check Engine
Examine a SYCL Application Graph x
Hotspot View View Performance Inefficiencies of Data-parallel Constructs
Find Issues Using Static Rule-check Engine x
Issue: Const Reference to a Host Pointer Used to Initialize a Buffer Issue: Host Pointer Accessor Used in a Loop Issue: Data Parallel Construct Inefficiency
Experimental Support for OpenMP* Applications x
Collecting Traces for OpenMP* Applications OpenMP* Constructs in the Per-Thread Task View OpenMP* Constructs in the Graph Canvas
Sample Trace Files x
code_generation Samples performance_analysis Samples
Minimize Analysis Overhead x
Collection Controls to Minimize Analysis Overhead Loop Markup to Minimize Analysis Overhead Filtering to Minimize Analysis Overhead Execution Speed/Duration/Scope Properties to Minimize Analysis Overhead Miscellaneous Techniques to Minimize Analysis Overhead
Analyze MPI Applications x
Model MPI Application Performance on GPU Control Collection with an MPI_Pcontrol Function
Manage Results x
Open a Result Rename an Existing Result Delete a Result Save Results to a Custom Location Work with Standalone HTML Reports Create a Read-only Result Snapshot Create a Result Snapshot Dialog Box Open a Result as a Read-only File in Visual Studio
Command Line Interface x
advisor Command Line Interface Reference Offload Modeling Command Line Reference Generate Pre-configured Command Lines
advisor Command Line Interface Reference x
advisor Command Action Reference advisor Command Option Reference
advisor Command Action Reference x
collect command create-project help import-dir mark-up-loops report snapshot version workflow
advisor Command Option Reference x
accuracy append app-working-dir assume-dependencies assume-hide-taxes assume-ndim-dependency assume-single-data-transfer auto-finalize batching benchmarks-sync bottom-up cache-binaries cache-binaries-mode cache-config cache-simulation cache-sources cachesim cachesim-associativity cachesim-cacheline-size cachesim-mode cachesim-sampling-factor cachesim-sets check-profitability clear config count-logical-instructions count-memory-instructions count-memory-objects-accesses count-mov-instructions count-send-latency cpu-scale-factor csv-delimiter custom-config data-limit data-reuse-analysis data-transfer data-transfer-histogram data-transfer-page-size data-type delete-tripcounts disable-fp64-math-optimization display-callstack dry-run duration dynamic enable-cache-simulation enable-data-transfer-analysis enable-task-chunking enforce-baseline-decomposition enforce-fallback enforce-offloads estimate-max-speedup evaluate-min-speedup exclude-files executable-of-interest exp-dir filter filter-by-scope filter-reductions flop force-32bit-arithmetics force-64bit-arithmetics format gpu gpu-carm gpu-kernel-of-interest gpu-sampling-interval hide-data-transfer-tax ignore ignore-app-mismatch ignore-checksums instance-of-interest integrated interval limit loop-call-count-limit loop-filter-threshold loops mark-up mark-up-list memory-level memory-operation-type mix mkl-user-mode model-baseline-gpu model-children model-extended-math model-system-calls module-filter module-filter-mode mpi-rank mrte-mode ndim-depth-limit option-file overlap-taxes pack profile-gpu profile-intel-perf-libs profile-jit profile-python profile-stripped-binaries project-dir quiet recalculate-time record-mem-allocations record-stack-frame reduce-lock-contention reduce-lock-overhead reduce-site-overhead reduce-task-overhead refinalize-survey remove report-output report-template result-dir resume-after return-app-exitcode search-dir search-n-dim select set-dependency set-parallel set-parameter show-all-columns show-all-rows show-functions show-loops show-not-executed show-report small-node-filter sort-asc sort-desc spill-analysis stack-access-granularity stack-stitching stack-unwind-limit stacks stackwalk-mode start-paused static-instruction-mix strategy support-multi-isa-binaries target-device target-gpu target-pid target-process target-system threading-model threads top-down trace-mode trace-mpi track-memory-objects track-stack-accesses track-stack-variables trip-counts verbose with-stack
Offload Modeling Command Line Reference x
run_oa.py Options collect.py Options analyze.py Options
Troubleshooting x
Error Message: Application Sets Its Own Handler for Signal Error Message: Cannot Collect GPU Hardware Metrics for the Selected GPU Adapter Error Message: Memory Model Cache Hierarchy Incompatible Error Message: No Annotations Found Error Message: No Data Is Collected Error Message: Stack Size Is Too Small Error Message: Undefined Linker References to dlopen or dlsym Problem: Broken Call Tree Problem: Code Region is not Marked Up Problem: Debug Information Not Available Problem: No Data Problem: Source Not Available Problem: Stack in the Top-Down Tree Window Is Incorrect Problem: Survey Tool does not Display Survey Report Problem: Unexpected C/C++ Compilation Errors After Adding Annotations Problem: Unexpected Unmatched Annotations in the Dependencies Report Warning: Analysis of Debug Build Warning: Analysis of Release Build
Reference x
Data Reference Dependencies Problem and Message Types Recommendation Reference User Interface Reference
Data Reference x
CPU Metrics Accelerator Metrics
Dependencies Problem and Message Types x
Dangling Lock Data Communication Data Communication, Child Task Inconsistent Lock Use Lock Hierarchy Violation Memory Reuse Memory Reuse, Child Task Memory Watch Missing End Site Missing End Task Missing Start Site Missing Start Task No Tasks in Parallel Site One Task Instance in Parallel Site Orphaned Task Parallel Site Information Thread Information Unhandled Application Exception
Recommendation Reference x
Vectorization Recommendations for C++ Vectorization Recommendations for Fortran
User Interface Reference x
Dialog Box: Corresponding Command Line Dialog Box: Create a Project Dialog Box: Create a Result Snapshot Dialog Box: Options - Assembly Editor Tab Dialog Box: Options - General Dialog Box: Options - Result Location Dialog Box: Project Properties - Analysis Target Dialog Box: Project Properties - Binary/Symbol Search Dialog Box: Project Properties - Source Search Pane: Advanced View Pane: Analysis Workflow Pane: Roofline Chart Pane: GPU Roofline Chart Project Navigator Pane Toolbar: Intel Advisor Annotation Report Window: Dependencies Source Window: GPU Roofline Regions Window: GPU Roofline Insights Summary Window: Memory Access Patterns Source Window: Offload Modeling Summary Window: Offload Modeling Report - Accelerated Regions Window: Perspective Selector Window: Refinement Reports Window: Suitability Report Window: Suitability Source Window: Survey Report Window: Survey Source Window: Threading Summary Window: Vectorization Summary
Window: Refinement Reports x
Tab: Dependencies Report Tab: Memory Access Patterns Report
Appendix x
Data Sharing Problems Notational Conventions Key Concepts Related Information
Data Sharing Problems x
Data Sharing Problem Types Problem Solving Strategies
Data Sharing Problem Types x
Incidental Sharing Independent Updates
Problem Solving Strategies x
Eliminate Incidental Sharing Synchronize Independent Updates Difficult Problems: Choosing a Different Set of Tasks Fix Problems in Code Used by Multiple Parallel Sites Memory That is Accessed Through a Pointer
Eliminate Incidental Sharing x
Examine the Task's Static and Dynamic Extent Verify Whether Incidental Sharing Exists Create the Private Memory Location Pointer Dereferences
Synchronize Independent Updates x
Synchronization Explicit Locking Assign Locks to Transactions Pitfalls from Using Synchronization
Key Concepts x
Glossary Parallelism
Parallelism x
Parallel Processing Terminology Add Parallelism Common Issues When Adding Parallelism Parallel Programming Implementations
Intel® Advisor User Guide

Examine Relationships Between Memory Levels

Accuracy Level

Medium

Enabled Analyses

Survey + Characterization (Trip Counts and FLOP, Call Stacks, Memory-Level) + Memory Access Patterns

Result Interpretation

In the Medium accuracy preset, the Intel® Advisor extends the basic Roofline capability and collects metrics for all memory levels and the callstack data, which allows you to analyze your application in more detail. Roofline chart uses the results of Memory Access Patterns analysis to understand what bounds the loop and build recommendations in Roofline Guidance.

For information about Memory Access Patterns data interpretation, refer to Investigate Memory Usage and Traffic.

NOTE:
This topic describes data as it is shown in the CPU Roofline report in the Intel Advisor GUI. You can also view the result in an HTML report, but data arrangement and panes may vary.

Memory-Level Roofline

The Memory-Level Roofline allows you to examine each loop at different cache levels and arithmetic intensities and provides precise insights into which cache level causes the performance bottlenecks.

The Memory-Level Roofline can help you to:

  • Determine which loops are limited by cache
  • Find inefficient access patterns
  • Locate loops that can benefit from vectorization or threading optimizations

To configure the Memory-Level Roofline chart:

  1. Expand the filter pane in the Roofline chart toolbar.
  2. In the Memory Level section, select the memory levels you want to see metrics for.

  3. Click Apply.
  4. In the Roofline chart, double-click a loop to examine how the relationships between displayed memory levels and roofs. Labeled dots are displayed, representing memory levels with arithmetic intensity for the selected loop/function; lines connect the dots to indicate that they correspond to the selected loop/function.

TIP:
By default, the Memory-Level Roofline chart is generated for the system cache configuration. You can also generate the chart for a custom cache configuration:
  1. Go to Project Properties > Trip Count and FLOP.
  2. In the Cache simulator field, click Modify.
  3. Click Add and enter/select the desired cache configurations.
  4. Re-run the Roofline with the Medium accuracy.

Memory-Level Roofline Data

Intel® Advisor collects integrated traffic data for all traffic types between a CPU and different memory subsystem using cache simulation. With this data, Intel® Advisor counts the number of data transfers for a given cache level and computes AI for each loop and each memory level.

Review the changes in the traffic from one memory level to another and compare it to respective to identify the memory hierarchy bottleneck for the kernel and determine optimization steps based on this information.

  • The vertical distance between memory dots and their respective roofline shows how much you are limited by a given memory subsystem. If a dot is close to its roof line, it means that the kernel is limited by the performance of this memory level.
  • The horizontal distance between memory dots indicates how efficiently the loop/function uses cache. For example, if L3 and DRAM dots are very close on the horizontal axis for a single loop, the loop/function uses L3 and DRAM similarly. This mean that it does not use L3 and DRAM efficiently. You can try to improve re-usage of data in the code to change arithmetic intensity for all loops/functions and improve application performance. For more precise advice, see the Roofline Guidance in the Code Analytics tab.

  • Arithmetic intensity determines the order in which dots are plotted, which can provide some insight into your code's performance. For example, the L1 dot should be the largest and first plotted dot on the chart from left to right. However, memory access type, latency, or technical issues can change the order of the dots. Continue to run the Memory Access Pattern analysis to investigate this issue.

To examine a specific loop in more details, select a dot on the chart and open the Code Analytics tab below the chart:

  • Review the amount of data transferred for the selected loop/function and a specific roof that bounds the loop in the Roofline pane. Use this pane to analyze deeper a selected loop/function:
    • It shows only roofs with number of threads, data types, and instructions mix used in the loop.
    • It identifies what exactly bounds the selected loop - memory, compute, or both memory and compute.
    • It determines exact roof that bounds the loop and estimates a potential speedup for the loop in the callout if you optimize it for this roof.

  • Review the memory metrics for different memory levels (L1, L2, L3 and DRAM) and the number of operations transferred (FLOP and INTOP) in the Data transfers and Bandwidth table. This indicates the amount of self data (excluding data from inner loops/functions) or total data (including data from inner loops/functions) transferred, memory level bandwidth, and percentage of memory used at each memory level.

    NOTE:
    Total data transfers are available only if you collect Roofline with Callstacks.

  • Review the amount of data processed at different memory levels for the selected loop in the Memory Metrics pane. The pane shows two histograms:
    • Review the time spent processing requests for each memory level reported in the Impacts histogram. A big value indicates a memory level that bounds the selected loop. Examine the difference between the two largest bars to see how much throughput you can gain if you reduce the impact on your main bottleneck. It also gives you a long-time plan to reduce your memory bound limitations as once you will solve the problems coming from the widest bar, your next issue will come from the second biggest bar and so on. Ideally, a developer would like to see the L1 as the most impactful memory in the application for each loop.
    • Review an amount of data that passes through each memory level reported in the Shares histogram.

    NOTE:
    Metrics in the Memory Metrics pane calculated for a dominant operation type in the selected loop (FLOAT or INT) and based on the total data aggregating all callctacks. Hover over the ? icon for the whole pane to see the tooltip that indicates the dominant type.

Roofline with Callstacks

Intel® Advisor basic Roofline model, the Cache-Aware Roofline Model (CARM), offers self data capability. Intel® Advisor Roofline with Callstacks feature extends the basic model with total data capability:

  • Self data = Memory access, FLOPs, and duration related only to the loop/function itself and excludes data originating in other loops/functions called by it

  • Total data = Data from the loop/function itself and its inner loops/functions

The total-data capability in the Roofline with Callstacks feature can help you:

  • Investigate the source of loops/functions instead of just the loops/functions themselves.

  • Get a more accurate view of loops/functions that behave differently when called under different circumstances.

  • Uncover design inefficiencies higher up the call chain that could be the root cause of poor performance by smaller loops/functions.

To view the callstacks, enable the With Callstacks checkbox in the Roofline chart.

To show/hide dot descendants:

  • Click a loop/function dot control to collapse descendant dots into the parent dot.

  • Click a loop/function dot control to show descendant dots and their relationship with visual indicators to the parent dot.

Roofline with Callstacks Chart Data

The following Roofline chart representation shows some of the added benefits of the Roofline with Callstacks feature, including:

  • A navigable, color-coded Callstack pane that shows the entire call chain for the selected loop/function, but excludes its callees

  • Visual indicators (caller and callee arrows) that show the relationship among loops and functions

  • The ability to simplify dot-heavy charts by collapsing several small loops into one overall representation

    Loops/functions with no self data are grayed out when expanded and in color when collapsed. Loops/functions with self data display at the coordinates, size, and color appropriate to the data when expanded, but have a gray halo of the size associated with their total time. When such loops/functions are collapsed, they change to the size and color appropriate to their total time and, if applicable, move to reflect the total performance and total arithmetic intensity.



Parent topic: Explore CPU/Memory Roofline Results

See Also

Compare CPU Roofline Results Use the Roofline Compare functionality to display Roofline chart data from other Intel® Advisor results or non-archived snapshots for comparison purposes to track optimization progress.
Level Two Title