RapidIO IP Core Resource Center

RapidIO MegaCore Functions

• RapidIO II MegaCore function complies with the RapidIO Specification Revision 2.2.
• Physical, transport, and logical layer separations (modular architecture)
• IDLE2 sequence - long control symbol
• 1.25, 2.5, 3.125, 5.0, and 6.25 Gbaud lane rates with 1x, 2x, and 4x link widths
• RapidIO MegaCore function complies with RapidIO Specification Revisions 1.3/2.1
• Physical, transport, and logical layer separations (modular architecture)
• IDLE1 sequence - short control symbol
• 1.25, 2.5, 3.125, and 5.0 Gbaud lane rates with 1x and 4X link widths

For device support details, such as lane rates, link widths, and speed grades, refer to the RapidIO MegaCore function user guides.

The solutions, which include configurable RapidIO IP cores and development boards, allow you to concentrate on the core functions of the system design by providing:

• Simple and fast protocol implementation
• Reduced design risks
• Shortened development times
• Platform designer for system interconnect

Documentation

• RapidIO II MegaCore Function User Guide
• RapidIO MegaCore Function User Guide
• MegaCore IP Library Release Notes
• Archive of intellectual property release notes

Application Notes

• AN 513: RapidIO Interoperability with TI 6482 DSP Reference Design
• AN 568: RapidIO Interoperability with TI 6488 DSP Reference Design
• AN 617: RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix® IV GX Devices

Reference Designs

• SRIO to TI 6482 DSP reference design
• SRIO to TI 6488 DSP reference design
• RapidIO dynamic data rate reconfiguration reference design for Stratix IV GX devices
• Design example: Maintenance Host to System Maintenance Agent bridge
• Design example: Customized Implementation Using Avalon®-ST Pass-Through Interface

Knowledge Database

The Knowledge Database provides support solutions, answers to frequently asked questions, and information about known issues regarding RapidIO.

See frequently viewed solutions:

• Does the SRIO MegaCore provide any platform to implement some custom logical layer functions or my own custom NREAD/NWRITE module?
• Why does the order of the SRIO link packets differ from the order in the application layer?
• Is the RapidIO capable of recovering from a cable pull and re-establishing a SRIO link?
• Can I connect the system maintenance Agent interface in my SRIO design to ground if I am not using it to reduce the overall logic element (LE) consumption?
• How does the waitrequest signal of the Avalon-MM I/O Agent port respond to a continuous write burst?

Development Kits

The following development kits are available for the RapidIO MegaCore function:

• Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit
• Intel® Arria® 10 GX FPGA Development Kit
• Intel® Stratix® 10 GX FPGA Development Kit
• Stratix® V DSP Development Kit
• Stratix® V GT Transceiver Signal Integrity Development Kit
• Stratix® V GX Transceiver Signal Integrity Development Kit
• Stratix® V GX FPGA Development Kit

Related Links

• Intel FPGA community
• Intel FPGA IP evaluation mode support
• Installation and licensing support resources
• Intel® FPGA Support Resources