Intel® SoC FPGA Bare-metal Developer Center

1. Prerequisites

Create Your My Intel Account

• Create your My Intel account from the My Intel page.
• Your My Intel account allows you to file service requests, register for classes, download software, access resources, training courses, and more.

Design Considerations

What is Bare-metal?

• Bare metal represents the actual register interfaces and hardware features of the processor system.
  
• Bare-metal development uses a software runtime environment that does not use an OS or an RTOS.
• In bare-metal configurations, the HPS of SoC FPGAs can be used. Intel offers HWLIBs that consist of high-level APIs and low-level macros that enable you to exercise most of the HPS peripherals.

Why Bare-metal?

• The advantages of using a bare-metal approach are:
• Absolute control of hardware
• Increased efficiency
• Minimal size (both flash and memory footprint)
• No dependency on other source codes or libraries
• Easier to formally prove correctness and perform code coverage analysis
• Other reasons for selecting bare-metal development are:
• Need to perform board bring-up and focus on one peripheral at a time
• Need to re-use existing legacy code that is already developed as bare-metal
• Lack of experience with an OS or RTOS

Bare-metal Considerations

To develop a bare-metal application for the HPS, you must be familiar with developing runtime capabilities to ensure that your application makes efficient use of the resources available in your CPU subsystem. Examples of what may be required are as follows:

• In-depth knowledge of the hardware platform
  
• Developing runtime capabilities to manage the process between the core and the cache subsystem if you want to fully utilize the CPU subsystem, as a typical bare-metal application uses only a single core
• Developing capabilities to manage and schedule processes, handle inter-process communications, and synchronize events within your application

If your scheduled project does not allow for effort it may take to become familiar with the above points, then it is recommended that you consider using a commercial Linux* or RTOS solution.

Design Flow Diagram

The typical design flow diagram for bare-metal development is shown below:

A summary of the flow is as follows:

• Start with a hardware design, which includes:
• HPS configuration: clock settings, pin multiplexing and configuration, DDR settings, connected peripherals, and so on.
• FPGA fabric contents: IP cores instantiated in the FPGA, and FPGA pin, memory controller, and phase-locked loop (PLL) configuration
• The hardware design is compiled with the Intel® FPGA Complete Design Suite tools, which generate the following files:

• SOF file: used to configure the FPGA fabric through various methods – external programmer, external flash, HPS bootloader, or even HPS application
• Handoff: contains information used by the Second Stage Bootloader Generator to create the bootloader that will be used on the HPS
• SOPCINFO file: can be used to automatically create header files with the FPGA soft IP addresses
• SVD file: contains information about the FPGA soft IP registers so that the ARM* Development Studio 5* (DS-5*) Intel SoC FPGA Edition debugger can show them in a user-friendly format during debugging
• User writes custom source code, with the aid of the HWLIBs, and potentially using the FPGA IP address header files
• User compiles the bare-metal application with the aid of the bare-metal compilers
• User debugs the bare-metal application by using the ARM DS-5 Intel SoC FPGA Edition

2. Getting Started

Select Target Board

• We recommend starting your development on an SoC Development Kit provided by Intel because the getting started bare-metal examples are targeted to run on those boards.
• To see the available SoC FPGA boards, visit Intel® FPGA Boards.

Install Intel SoC FPGA EDS

• The Intel SoC FPGA EDS provides essential tools that are required for all SoC FPGA development, including bare metal. Refer to the Embedded Software and Tools for Intel® SoC FPGA for more details.
• Download the Intel® SoC FPGA Embedded Development Suite (SoC EDS) Pro Edition from the FPGA Download Center.
• Installation process and installing the tools for Intel SoC FPGA EDS.
• If the ARM DS-5 Intel SoC FPGA Edition is used for debugging and/or tracing bare-metal applications, you will need to obtain a license. The license is typically included with your Intel SoC FPGA Development Kit purchase. Refer to the Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide License Setup Instructions.

Select Build Tools

• The Intel SoC FPGA EDS provides the following bare-metal build tools:
• Intel SoC FPGA version of Mentor CodeSourcery – GCC-based, no license required
• ARM Compiler 5 – license included with the Intel SoC FPGA EDS license
• Other build tool suites targeting ARM platforms can be used – go to the Ecosystem for Intel® FPGA and Intel® SoC FPGA Devices.
• The getting started example projects are available for both GCC and ARMCC compilers provided as part of the Intel SoC FPGA EDS.

Select Debug and Trace Tools

• The Intel SoC FPGA EDS includes the ARM DS-5 Intel SoC FPGA Edition, which fully supports debugging and tracing of bare-metal programs – license required
• The getting started example projects are using ARM DS-5 Intel SoC FPGA Edition for both debugging and tracing

Exercise the Getting Started Application

• A sample getting started application is available for Cyclone V, Arria V, and Intel® Arria® 10 devices, supporting both ARMCC and GCC compilers.
• The sample application exercises the following
• HPS SDRAM, MMU, caches,
• HPS timers, interrupts
• HPS-to-FPGA bridges
• FPGA soft IP: SysID
• FPGA interrupts
• Find the documentation and downloads to the version that you need on on Rocketboards.org on topic SoCEDS and ARM Development Studio.

3. Creating Your Own Project

Types of Bare-Metal Projects

There are two different types of projects that can be managed by the ARM DS-5 Intel SoC FPGA Edition:

• Makefile-based projects: the project is managed by manually editing the makefile, and the ARM DS-5 Intel SoC FPGA Edition just calls 'make all' and 'make clean' on that makefile to build and to clean your project, respectively.
  
• Plugin-based projects: The ARM DS-5 Intel SoC FPGA Edition completely manages your project, including files to compile, compiler options, building, and cleaning.

The advantage of a makefile-based project is that it can invoke any other tools, not just the bare-metal compiler, thus offering more flexibility. The only advantage of using a plugin-based project is that the settings are easily accessible from the ARM DS-5 Intel SoC FPGA Edition graphical interface as opposed to editing the makefile with a text editor.

Recommended Method to Create Your Own Project

We recommend getting started using the provided script to automatically create your plugin-based or makefile-based project.

The script performs the following actions:

• Create project folder
• Create C project file, with all the required compilation settings
• Create a simple main.c file, that simply prints a 'hello world' message
• Bring in all the relevant HWLIBs files
• Create the system.h file having the base addresses of the FPGA fabric peripherals (requires the Intel® Quartus® Prime software to be first installed, otherwise this step will be skipped)
• Create a debug configuration for debugging the application
• Create a debug configuration for running the bootloader [optional]
• Create an external tool launcher for configuring FPGA fabric from the ARM DS-5 Intel SoC FPGA Edition [optional]
• Create an external tool launcher for re-generating the system.h file when needed [optional]

Note that all the getting started projects described in the Getting Started section were created using this method.

Alternative Methods to Create Your Project

You can also create your own projects using the following alternatives:

• Option 1: Manually create a makefile, then refer to Arm* Development Studio* for Intel® SoC FPGA Edition to find insructions to create the project in the ARM DS-5 Intel SoC FPGA Edition as a makefile-based project. Manually creating the makefile is beyond the scope of this guide, and requires you to familiarize yourself with all the build tools and their options. If a makefile is required, the recommended method is to use the provided script to create it.
  
• Option 2: Manually create a plugin-based project from scratch. This consists of manually reproducing the procedure that the provided script follows in order to create the project. Note that the script offers more features, and is the recommended method to create your project. This option is documented for reference only.
• Option 3: Start with an existing project and modify it to suit your needs. This can be done especially for short tests and experiments but this method is not recommended.

4. Examples

Getting started bare-metal applications

Table A. Targeting Intel SoC Development Boards and exercising:

• HPS SDRAM
  
• HPS MMU and caches
• HPS timer, with interrupts
• FPGA IP: SysID and PIO – push buttons, dual in-line package (DIP) switches, and LEDs
• FPGA interrupts

Bare-metal examples included with the Intel SoC FPGA EDS

Table B. Targeting Intel SoC Development Boards and available from <SoC FPGA Installation Folder>\embedded\examples\software\:

Additional bare-metal examples

Table C. Targeting Intel SoC Development Boards and available from Design Examples page, all using the GCC compiler:

How to Implement Execute in Place (XIP) on Cyclone V FPGAs

Refer to the Cyclone V QSPI XIP Example Design page on Intel FPGA Wiki for complete instructions on how to run a bare-metal application from QSPI flash.

How to Boot Bare-Metal Applications on Cyclone V FPGAs

Refer to Application Note 709, Boot Examples chapter for examples on booting a Cyclone V SoC bare-metal application from:

• SD/MMC
  
• QSPI
• FPGA

5. Additional Resources

Support Resources

Help is just a click away! The Support Resources provides online technical resources, from training classes to design examples to forums, that guide you through every step of the design process.

Knowledge Base

The Knowledge Base provides a vast number of support solutions, reference articles, error messages, and troubleshooting guides, and it is also fully searchable.

Intel Community

Intel Community is a community website enabling collaboration between Intel FPGA users. Check out the "Embedded Design Suite (EDS)" and "SoC Discussion" sections. Use the search engine to find relevant material. You are also are encouraged to update and contribute.

Training Classes

Below are foundational training classes that you can take before starting your bare-metal development.

Learning -Intel SoC FPGA EDS User Guide

The SoC EDS User Guide is a foundational document describing all the Intel SoC FPGA EDS tools and components. We highly recommend reviewing the following sections relevant to bare-metal development:

Learning - Intel SoC FPGA EDS Getting Started Guides

The SoC EDS Getting Started Guides on the Intel FPGA Wiki is a set of foundational basic instructions to help you easily get started with the Intel SoC FPGA EDS.

Additional Documentation and Resources

Technical Reference Manuals

Technical reference manuals contain detailed descriptions of the hardware, including the behavior, base addresses, interrupt mapping, and control/status registers for all the peripherals.

SoC Documentation Pages

The SoC documentation pages conveniently provide a single location to access all relevant SoC documentation, such as tecnhical reference manuals, datasheets, and application notes.

Additional Resources

Related Links

• Embedded Software Developer Center
• Intel® FPGA Support Resources
• Intel® FPGA Development Tools
• RocketBoards