SoC FPGA Bootloader Developer Center
SoC FPGA Bootloader Developer Center provides the available SoC bootloaders with main characteristics, how to get started, and additional resources.
SoC FPGAs use a bootloader to load and run the end user application on the hard processor system (HPS). The end user application may be a simple bare-metal application or a complex operating system like the Linux* operating system.
This page describes what a bootloader is, lists the available boot loaders and their main characteristics, describes how to get started with the bootloaders, and lists resources for Agilex™ 7, and Agilex™ 5, Stratix® 10 SoC, Arria® 10 SoC, Cyclone® 10 GX SoC, Cyclone® 10 LP SoC, Arria® V SoC, Cyclone® V SoC devices.
Get additional support for Agilex™ 7 Software Development, and Agilex™ 5 Software Development, step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.
For other devices, search the Device and Product Support Collections.
1. What is a Bootloader
Bootloader Definition
When an SoC device boots up, a piece of software called the BootROM is first run. For several reasons, the BootROM has the following limited functionality:
- It needs to fit in the on-chip ROM so it has to be small
- It is very expensive to change so it has to be very robust, which implies less features
- It does not know how the system was configured so it cannot bring up everything
The end user application on the other hand is typically large and requires the system to be configured as desired by the end user before it can run.
The bootloader's job is to bridge the gap between the BootROM and the end user application.
Single Stage Bootloader
Typical Bootloader Tasks
- Configuring the pin multiplexing and pin settings, such as slew rate, voltage, and pull-up/pull-down
- Configuring the clocks in the clock tree
- Bringing up and calibrating the SDRAM
- Initializing the flash memory
- Configuring the FPGA fabric
- Loading the end application from the flash memory
- Passing control to the end application
Besides the features listed above, bootloaders also offer the following advanced features that can enable more complex deployment and more convenient development:
- Network access that brings in the end user application from the cloud.
- Debugging tools that enable more convenient diagnosis of issues.
- Command-line interface for interactive commands.
- Application running a framework that can enable simple end user applications to be loaded and run to completion by the bootloader. After the application completes, the control is passed back to the bootloader.
Bootloaders for SDM-Based Devices
For Agilex™ 7 SoCs and Agilex™ 5 SoCs, and Stratix® 10 SoCs a two-stage bootloader is typically used. The first small bootloader stage is part of the FPGA configuration bitstream and is loaded by the secure device manager (SDM) into the HPS on-chip RAM, while the second larger bootloader stage needs to be stored in a location that is accessible by the HPS.
Multi-Stage Bootloaders
Sometimes the bootloader process can be split into multiple stages, typically two.
For Cyclone® V SoCs, the BootROM can only load a boot loader of up to 64 KB in size because the SDRAM is not yet brought up at that stage. Similarly for Arria® 10 SoCs the BootROM can only load a bootloader of up to 256 KB in size. Because of these size limitations, advanced features such as networking or complex filesystem access cannot be accomplished. If such features are desired, the first stage of the bootloader brings up the SDRAM and then loads a second stage with more functionality. A two-stage bootloader is the default option for Cyclone V SoCs, Arria® V SoCs, and Arria® 10 SoCs.
2. Hardware Handoff
Handoff Overview
All SoC FPGA projects start with a hardware project where various system settings listed below are configured by the user that will impact the HPS.
- Pin multiplexing
- Pin settings
- SDRAM settings
- Clock settings
It is the bootloader's job to apply these settings and the process of the bootloader receiving these settings is called the hardware-to-software handoff.
Depending on the exact bootloader and SoC device family, the handoff can take various below forms.
- For Cyclone V and Arria V SoCs, the handoff is a combination of XML files, binary files, and source code files, which are converted to source code and then compiled into the bootloader
- For Arria 10 SoCs, the handoff is contained in a single XML file that is converted to a device tree file and used by the bootloader
- For Agilex 7 SoCs, and Agilex 5 SoCs, and Stratix 10 SoCs the handoff information is part of the FPGA configuration bitstream
The primary method of entering or changing the handoff information is through editing them in the Quartus® Platform Designer.
In addition to the handoff information, the bootloaders also have various settings that can be selected by the user through the following methods.
- Editing the bootloader source code
- Editing the bootloader device tree when a device tree is used
Agilex™ 7, and Agilex™ 5, Stratix® 10 SoC Handoff
- For Agilex 7, and Agilex 5, Stratix 10 SoC the handoff information is part of the FPGA configuration bitstream.
Arria® 10 SoC Handoff
- For Arria 10 SoCs, the handoff is contained in a single XML file that is converted to a device tree file and used by the bootloader
Cyclone® V SoC and Arria® V SoC Handoff
- For Cyclone V and Arria V SoCs, the handoff is a combination of XML files, binary files, and source code files, which are converted to source code and then compiled into the bootloader
3. Available Bootloaders
Overview of Available Bootloaders
Available bootloaders, types of licenses, supported SoCs, and availability of two-stage support.
| Device | Bootloader |
License Type |
Description |
|---|---|---|---|
Agilex™ 7 Agilex™ 5 Stratix® 10 |
ATF | BSD | The ARM Trusted Firmware (ATF) is a reference implementation of secure world software for ARMv8-a, implementing various ARM interface standards, such as Trusted Board Boot Requirements (TBBR) and Secure Monitor Call (SMC). The ATF is developed collaboratively under a BSD license, which allows convenient development and deployment. The source code for SoC FPGA port of ATF can be accessed at https://github.com/altera-opensource/arm-trusted-firmware. |
Agilex™ 7 Agilex™ 5 Stratix® 10 Arria® 10 Arria® V Cyclone® V |
U-Boot |
GPL |
U-Boot is a bootloader that is widely used by the industry and offers numerous capabilities:
U-Boot is developed under a general-public licence (GPL) so any contributions that are made to a product that is being delivered to the public must also be made public. The U-Boot source code is available at the U-Boot SoC FPGA page on the GitHub website. The main generic U-Boot home page is located at the Das U-Boot -- the Universal Boot Loader web page. |
5. Resources
| Resource Type | Agilex™ 7 | Agilex™ 5 | Stratix® 10 SoC | Arria® 10 SoC and Cyclone® V SoC |
|---|---|---|---|---|
| Design Examples | F-Series SoC Development Kit |
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| User Guide | HPS Boot User Guide | HPS Boot User Guide | ||
| Source Code | Altera SoC FPGA U-Boot on GitHub |
Altera SoC FPGA U-Boot on GitHub |
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