altufm_parallel Intel® FPGA IP
The altufm_parallel Intel® FPGA IP implements user non-volatile memory for MAX® II devices using the parallel interface protocol. The altufm_parallel Intel® FPGA IP is available for MAX® II and MAX® V devices only.
Intel recommends instantiating this function with the IP Catalog.
Note:
- For this Intel® FPGA IP, the IP Catalog generates output files with multiple entities or modules. The top-level entity or module is located at the bottom of the file.
- When performing a VHDL simulation with a , you must assert the devpor signal at time 0 to reset the registers in the logic cells before starting a VHDL simulation.
- You can use the Assignment Editor to add, change, or delete assignments and assignment values for Intel® FPGA IP.
- When you create the Intel® FPGA IP, you can use the IP Catalog to generate a netlist for third-party synthesis tools.
Note: More information is available on the altufm_parallel Intel® FPGA IP on the Altera
website.