RES-50002: Asynchronous Reset is Insufficiently Synchronized

Description

Violations of this rule identify asynchronous reset synchronizer chains that are one register long. Such chains are too short to prevent metastability.

Figure 1. Single-Stage Reset Synchronizer Chain Example.. The following figure shows an example of a asynchronous reset synchronizer chain with only one stage, which triggers the RES-50002 Design Assistant violation. To prevent a violation, the register must be followed by at least one other register also latched by clk and reset by the same asynchronous reset signal.

Recommendation

Ensure that all asynchronous reset synchronizer chains contain at least two registers. Refer to the recommendations of RES-50001 - Asynchronous Reset Is Not Synchronized for instructions on how to form such a chain.

Figure 2. Multiple-Stage Reset Synchronizer Chain Example.. The following figure shows an example of a asynchronous reset synchronizer chain with two stages.

Severity

High

Tags

Tag Description
synchronizer Design rule checks related to synchronizer chains.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel®Agilex™