Input Ports

dataa[]

Yes

Data input to the memory.

Input port LPM_WIDTH wide.

datab[]

Yes

Data input to the memory.

Input port LPM_WIDTH wide.

addressa[]

Yes

Address input to the memory.

addressb[]

Yes

Address input to the memory.

wea

Yes

Write Enable input.

web

Yes

Write Enable input.

clock

Yes

Positive-edge-triggered clock.

clockx2

Yes

Positive-edge-triggered clock operating at twice the frequency of clock.