csdpram Intel® FPGA IP

Parameterized cycle-shared dual-port RAM Intel® FPGA IP. The csdpram function uses DFFE primitives. Intel strongly recommends using synchronous rather than asynchronous RAM functions. The csdpram Intel® FPGA IP is provided for backward compatibility only.

Note:
  • The csdpram function is not available for VHDL designs.
  • You can use the Assignment Editor to add, change, or delete assignments and assignment values for Intel® FPGA IP.
  • When you create your Intel® FPGA IP, you can use the IP Catalog to generate a netlist for third-party synthesis tools.