Running Gate-Level Functional Simulation with the ModelSim® - Intel® FPGA Edition GUI
- If you have not already done so, set up a project with the ModelSim® - Intel® FPGA Edition software.
- To compile the Verilog HDL or VHDL Design Files and testbench files (if you are using a testbench):
- To load the design:
- Perform the functional simulation in the ModelSim® - Intel® FPGA Edition software.