All Logic Options Sorted alphabetically. Add D and Q Ports of Register Node to Simulation Output Waveforms logic option Add Pass-Through Logic to Inferred RAMs logic option Add to Simulation Output Waveforms logic option Alias logic option Allow Any RAM Size For Recognition logic option Allow Any ROM Size For Recognition logic option Allow Any Shift Register Size For Recognition logic option Allow Synchronous Control Signals logic option Allow Shift Register Merging Across Hierarchies logic option Always Enable Input Buffers logic option Auto Carry Chains logic option Auto Clock Enable Replacement logic option Auto Delay Chains logic option Auto DSP Block Replacement logic option Auto Global Clock logic option Auto Global Output Enable logic option Auto Global Register Control Signals logic option Auto Merge PLLs logic option Auto Open-Drain Pins logic option Auto Packed Registers logic option Auto RAM Block Balancing logic option Auto RAM Replacement logic option Auto Shift Register Replacement logic option Auto Gated Clock Conversion logic option Auto Global Memory Control Signals logic option Auto Logic Cell Insertion logic option Auto Parallel Expanders logic option Auto RAM to Logic Cell Conversion logic option Auto RAM to MLAB Conversion logic option Auto Register Duplication logic option Auto Resource Sharing logic option Auto ROM Replacement logic option Auto Turbo Bit logic option Definition Automatic Asynchronous Signal Pipelining -- Allow Asynchronous Signal that Fans Out to Synchronous Inputs logic option Automatic Asynchronous Signal Pipelining Register Reach logic option Block Design Naming logic option Carry Chain Length logic option CKn/CK Pair logic option Clock MUX Protection logic option Current Strength logic option Clamping Diode logic option Create Debugging Nodes for IP Cores logic option D1 Delay (I/O buffer to input register) logic option D2 Delay (I/O buffer to input register or internal cells) logic option D3 Delay (I/O buffer to internal cells) logic option D4 Delay (DQS Delay Chain) logic option D5 OCT Delay (OCT to I/O buffer) logic option D5 Delay (output register to I/O buffer) logic option D6 Delay (output register to I/O buffer) logic option D6 OCT Delay (OCT to I/O buffer) logic option D6 Output Enable Delay (output enable register to I/O buffer) logic option Data[0] Pin logic option DCLK Pin logic option Delay from Output Register to Output Pin logic option Disable Design Assistant Rule logic option Disable Register Merging logic option Disable Register Merging Across Hierarchies logic option Disable Message logic option DQ Group logic option DQS Bus to Input Register Delay logic option DQS Frequency logic option DQSn/DQS Pair logic option DSP Block Balancing logic option Dynamic Termination Control Group logic option EDA Formal Verification Hierarchy logic option Enable Bus-Hold Circuitry logic option Enable Design Assistant Rule logic option Enable Message logic option Electromigration Current logic option Enable Beneficial Skew Optimization logic option Enable D1 Fine Delay (I/O buffer to input register) logic option Enable D5 Fine Delay (output register to I/O buffer) logic option Enable D4 Fine Delay (DQS Delay Chain) logic option Enable D6 Fine Delay (output register to I/O buffer) logic option Enable D6 Output Enable Fine Delay (output enable register to I/O buffer) logic option Enable Fine Delay Resolution on T11 Delay (DQS Post-Amble Delay) logic option Equivalent RAM and MLAB Paused Read Capabilities logic option Equivalent RAM and MLAB Power Up logic option Exclusive I/O Group logic option External LVDS Receiver Uses DPA logic option External Pin Connection logic option Extract Verilog State Machines logic option Extract VHDL State Machines logic option Far capacitance (in farads) logic option Far differential resistance (in ohms) logic option Far-End Measurement Voltage logic option Far pull-down resistance (in ohms) logic option Far series resistance (in ohms) logic option Far transmission line distributed capacitance (in farads/inch) logic option Far transmission line distributed inductance (in henrys/inch) logic option Far transmission line length (in inches) logic option Far pull-up resistance (in ohms) logic option Fast Input Register logic option Fast OCT Register logic option Fast Output Enable Register logic option Fast Output Register logic option Final Placement Optimizations logic option Fitter Aggressive Routability Optimizations logic option Force Use of Synchronous Clear Signals logic option Force Fitter to Avoid Periphery Placement Warnings logic option Force Fractured Mode ALM Implementation logic option Force Merging of PLL Clock Fanouts logic option Force Merging of PLLs logic option Force Non-Fractured Mode ALM Implementation logic option Force PLL Output Counter logic option Global Signal logic option Global Signal CLKCTRL Location logic option GXB 0 PPM core clock setting logic option GXB Dedicated Refclk Pin Termination logic option GXB I/O Pin Termination logic option GXB TX PLL Reconfiguration Group Setting logic option GXB VCCA Voltage logic option GXB VCCR VCCT Voltage logic option HDL Initial Fan-out Limit logic option HDL Message Level logic option Ignore CARRY Buffers logic option Ignore CASCADE Buffers logic option Ignore GLOBAL Buffers logic option Ignore LCELL Buffers logic option Ignore Maximum Fan-Out Assignments logic option Ignore ROW_GLOBAL Buffers logic option Ignore SOFT Buffers logic option Ignore translate_off and synthesis_off Directives logic option Ignore Verilog Initial Constructs logic option Implement as Clock Enable logic option Implement as Output of Logic Cell logic option Import File Name logic option In-System Programming Clamp State logic option Input Delay from Pin to DDIO Low Capture Input Register logic option Input Delay from Pin to Input Register logic option Input Delay from Pin to Internal Cells logic option Input Delay from Dual-Purpose Clock Pin to Fan-out Destinations logic option Input Termination logic option Input Reference logic option I/O Maximum Toggle Rate logic option I/O Placement Optimizations logic option I/O Standard logic option Iteration limit for constant Verilog loops logic option Iteration limit for non-constant Verilog loops logic option Insert Additional Logic Cell logic option Keep Synchronous Clear/Preset Behavior for DDIO Input When Unmap I/O WYSIWYG Primitives logic option Limit AHDL Integers to 32 Bits logic option Definition Logic Cell Insertion logic option Manual Logic Duplication logic option Match PLL Compensation Clock logic option Maximum Fan-Out logic option Maximum Number of LABs logic option Maximum Number of M4K/M9K/M20K/M10K Memory Blocks logic option Maximum DSP Block Usage logic option Memory Interface Data Pin Group logic option Memory Interface Delay Chain Configuration logic option Merge TX PLL Driven by Registers with Same Clear logic option Migration Packed Registers logic option Migration RAM Information logic option Migration Swapped Ports logic option Near capacitance (in farads) logic option Near differential resistance (in ohms) logic option Near-End Measurement Voltage logic option Near series resistance (in ohms) logic option Near pull-down resistance (in ohms) logic option Near pull-up resistance (in ohms) logic option Near transmission line distributed capacitance (in farads/inch) logic option Near transmission line distributed inductance (in henrys/inch) logic option Near transmission line length (in inches) logic option Netlist Optimizations logic option NOT Gate Push-Back logic option Number of Removed Registers Reported in Synthesis Report logic option Number of Inverted Registers Reported in Synthesis Report logic option Optimization Technique logic option Optimize Design for Metastability logic option Optimize IOC Register Placement for Timing logic option Optimize Timing logic option Optimize Timing for ECOs logic option Output Buffer Delay logic option Output Buffer Delay Control logic option Output Enable Group logic option Output Enable Pin Delay logic option Output I/O Timing Endpoint logic option Output Pin Load logic option Output Termination logic option Passive Resistor logic option Partition Hierarchy logic option Perform Asynchronous Signal Pipelining logic option Perform Register Duplication for Performance logic option Perform Register Retiming for Performance logic option Perform WYSIWYG Primitive Resynthesis logic option Placement Effort Multiplier logic option PLL Automatic Self Reset logic option PLL Bandwidth logic option PLL Channel Spacing logic option PLL Compensation logic option PLL Compensation Mode logic option PLL External Feedback Board Delay logic option PLL Ignore Migration Devices logic option PLL Output Clock Frequency logic option PLL PFD Clock Frequency logic option PLL Type logic option PLL VCO Clock Frequency logic option Preserve PLL Counter Order logic option Programmable Differential Output Voltage (VOD) logic option Power Analyzer Report Power Dissipation logic option Power Analyzer Report Signal Activity logic option Power Input File Settings logic option Power Optimization (Analysis and Synthesis Settings Page) logic option power optimization logic option (Advanced Settings) Power Static Probability logic option Power Toggle Rate logic option Power Toggle Rate Percentage logic option Power-Up Don't Care logic option Power-Up Level logic option Preserve Fan-out Free Register Node logic option Preserve Registers logic option Programmable Power Maximum High-Speed Fraction of Used LAB Tiles logic option Programmable Power Technology Optimization logic option Programmable Pre-emphasis logic option Regenerate Full Fit Report During ECO Compiles logic option Remove Redundant Logic Cells logic option Reserve Pin logic option Remove Duplicate Registers logic option Restructure Multiplexers logic option Router Timing Optimization Level logic option Report Parameter Settings logic option Safe State Machine logic option SCE Pin logic option SDO Pin logic option Shift Register Replacement - Allow Asynchronous Clear Signal logic option Show Setup and Hold Time Violations logic option Show "X" on Timing Violation logic option Slew Rate logic option Speed Optimization Technique for Clock Domains logic option State Machine Processing logic option Strict RAM Replacement logic option Synchronization Register Chain Length logic option Synchronizer Identification logic option Synthesis Effort logic option Definition T11 Delay (DQS post-amble delay) logic option T4 Delay (Output register to switch multiplexer) logic option T8 Delay (DQS to input register) logic option T8 Delay (NDQS to input register) logic option Termination Control Block logic option Termination voltage (in volts) logic option Timing-Driven Synthesis logic option Treat Bidirectional Pin as Output Pin logic option Turbo Bit logic option Use Checkered Pattern as Uninitialized RAM Content logic option Virtual Pin Clock logic option Virtual Pin logic option Weak Pull-Up Resistor logic option