A logic option that specifies the capacitive load, in picofarads
(pF), on an output pin for each I/O standard. When you specify this
option, you change the tCO of the output pin. You use this
option when you want the board load to be different from the
default value reported by the Intel® Quartus® Prime software in the
Output Pin Load for Reported TCO section of the Compilation
report. The default is 0 pF.
Important: Important: The Intel® Quartus® Prime software
does not recognize this option if it is applied to anything other
than an output or bidirectional pin, or if Advanced I/O Timing is
enabled. If Advanced I/O Timing is enabled, you can specify the
capacitive load with the Far capacitance logic option.
Important: Important: A differential I/O standard
uses two pins, one for the positive end and one for the negative
end. The Intel® Quartus® Prime software allows you to specify different
OUTPUT_PIN_LOAD
values on the positive end and the negative end. However, in most
cases, specifying different capacitive loading on the positive and
negative ends causes an adverse effect on the rise/fall timing of
the differential I/O pins. Therefore, for differential pins, Intel recommends specifying
the same OUTPUT_PIN_LOAD
on both the positive and negative ends as shown in the following
example: set_instance_assignment
-name OUTPUT_PIN_LOAD 20 -to "diff_output[0]" set_instance_assignment
-name OUTPUT_PIN_LOAD 20 -to "diff_output[0](n)" If a non-default OUTPUT_PIN_LOAD
value is specified for only one end, the Intel® Quartus® Prime software
uses the default OUTPUT_PIN_LOAD
value for the end that is not specified. For example, if you
specify set_instance_assignment
-name OUTPUT_PIN_LOAD 20 -to "diff_output[2]" for the
positive end, the Intel® Quartus® Prime software uses the default OUTPUT_PIN_LOAD
value, dependent on the I/O standard (for example, 0 pF for the
LVDS I/O
standard), for the negative end.
The Output Pin Load
logic option is useful for accurate modeling of tCO and power usage.
Note: Notes:
For more information on device specific output delay derating
factors and tCO loads, refer to individual
device family data sheets, which are available from the Literature
section of the Altera website Definition.
The Output Pin Load logic option can also be
set in the Pin Planner.
The value you enter for the output pin load should be the
loading value for the board trace capacitance and target load
capacitance. The Intel device pin/package capacitance is already
factored in the output pin load value.
The Intel® Quartus® Prime software uses the following equation to
determine the changes in the output delay and depends on the
specified Output Pin Load option:
output_delay = default_output_delay +
((output_pin_load - default_output_load) * derating
factor)
Capacitive loading is available for supported
device (MAX® II, and
MAX® V) families.
| Scripting
Information |
Keyword: output_pin_load
Settings:<integer>
Legal
values: 0 - 10000
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