Stratix IV Definition

An Intel device family based on a scalable architecture. The Stratix^® IV family includes Stratix^® IV GX and Stratix^®IVGT devices, which contain dedicated gigabit transceiver block (GXB) circuitry and PCI Express hard IP blocks, and Stratix^® IV E devices, which do not contain these blocks.

Stratix^® IV GX devices have dedicated gigabit transceiver block (GXB) circuitry that includes up to 36 high-speed clock data recovery (CDR) technology-based transceiver channels with physical coding sublayer (PCS) and physical medium attachment (PMA) at serial data rates of up to 8.5 Gbps. Stratix^®IVGT devices provide up to 48 high-speed transceiver channels at serial data rates of up to 11.3 Gbps.

Stratix^®IVdevices provide dedicated circuitry that supports differential I/O standards at up to 1.6Gbps when using dynamic phase alignment (DPA). All Stratix^® IV devices also provide enhanced PLLs, fast PLLs, and auxiliary transmit (ATX) PLLs; and regional, dual-regional, global, interquad, and periphery clock networks to increase performance, and provide advanced clock interfacing and clock-frequency synthesis.

Stratix^®IV family devices have dedicated circuitry to support physical layer functionality for serial protocols, such as PCI Express (PIPE) Gen1 and Gen2, Gigabit Ethernet, Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken. These protocols provide high-speed communication with application-specific standard products (ASSPs), application-specific integrated circuits (ASICs), and other programmable logic devices (PLDs). You can use both PCI Express hard IP and PCI Express soft IP to implement the physical layer, data link layer, and transaction layer of the PCI Express protocol stack. The PCI Express hard IP uses embedded dedicated logic to implement the PCI Express protocol stack.

Stratix^®IV family devices provide up to 12 PLLs for each device. Stratix^®IV family PLLs are capable of implementing real-time reconfiguration, clock switchover, advanced clock multiplication parameters, and fine-grain phase shifting.

Stratix^®IV family devices support numerous single-ended and differential I/O standards.

The Stratix^®IV family device architecture supports the TriMatrix Memory architecture, consisting of three RAM block sizes, which are the M144K and M9K memory blocks, and the MLAB. M144K and M9K memory blocks implement single-port, dual-port, and true dual-port memory. MLABs implement single-port and dual-port memory. Stratix^®IV family devices offer support for remote configuration updates. Stratix^®IV family devices also contain embedded DSP blocks that enable efficient implementation of high-performance filters and multipliers. The Adaptive Logic Module (ALM) of the Stratix^®IV family device architecture provides advanced features with efficient logic utilization.

The memory blocks of Stratix^®IV family devices can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port, and single-port RAM; ROM; FIFO buffers; and shift registers. These blocks can also emulate SERDES functions for low-speed LVDS channels. In addition, Stratix^®IV family device I/Os have dedicated circuitry to assist with the implementation of high-speed interfaces to external memory devices such as double data rate (DDR) SDRAM, DDR II SDRAM, DDR III SDRAM, quad data rate (QDR) II SRAM, and RLDRAM II.