I/O standards Definition
Standards that uniquely define the input and output (VCCIO) voltage, reference VREF voltage (if applicable), and the types of input and output buffers used for I/O pins.
The following table lists the I/O standards that are available, and the device families that support them. The table also lists the Intel® Quartus® Prime Settings File (.qsf) settings keyword for each I/O standard.
|
I/O Standard |
Device Family Support |
QSF Keyword |
|---|---|---|
|
1.2-V |
supported device (Stratix® V , Intel® MAX® 10, MAX® V,Arria® V series, and Cyclone® V series) families |
"1.2 V", "1.2V", "1.2-V" |
|
1.2-V HSTL Class I and II |
supported device (Intel® MAX® 10, Arria® series, Cyclone® IV , Cyclone® V , Stratix® IV, and Stratix® V ) families |
"1.2- V HSTL", "1.2- V HSTL Class I", "1.2- V HSTL Class II" |
|
1.2-V HSUL |
supported device (Intel® MAX® 10, Intel® Arria® 10 ,Arria® V , Cyclone® V , and Stratix® V ) families |
"1.2-V HSUL" |
|
1.2-VPCML |
supported device (Arria® series, Cyclone® IV GX, Stratix® IV, and Stratix® V ) families |
"1.2- V PCML" |
|
1.4-V PCML |
supported device (Stratix®IV, and Stratix®V) families |
"1.4-V PCML" |
|
1.5-V |
All Intel devices |
"1.5 V", "1.5V", "1.5- V" |
|
1.5-VHSTL Class I |
supported device (Intel® MAX® 10, Arria® series, Cyclone® IV , and Stratix® series) families |
"1.5- V HSTL Class I", "HSTL Class I" |
|
1.5-VHSTL Class II |
supported device (Arria® series, Cyclone® IV , and Stratix® series) families |
"1.5- V HSTL Class II", "HSTL Class II" |
|
1.5-VPCML |
supported device (Cyclone® IV GX, Stratix® IV, and Stratix® V ) families |
"1.5- V PCML" |
|
1.8V |
All Intel devices |
"1.8 V", "1.8V", "1.8- V" |
|
1.8-V HSTL Class I and II |
supported device (Intel® MAX® 10, Arria® series, Cyclone® IV , and Stratix® series) families |
"1.8- V HSTL Class I", "1.8- V HSTL Class II" |
|
2.5-V |
All Intel device families supported by the Intel® Quartus® Prime software |
"2.5 V", "2.5V", "2.5- V" |
|
2.5 V LVDS |
Arria® V series |
LVDS |
|
2.5-V PCML |
supported device (Cyclone® IV GX, Stratix® IV, and Stratix® V ) families |
"2.5-V PCML" |
|
2.5-V Schmitt Trigger Input |
MAX® V devices |
"2.5V Schmitt Trigger Input" |
|
3.0-V LVCMOS |
supported device (Arria® V, Cyclone® IV , MAX® V, and Cyclone® V ) families |
"3.0-V LVCMOS", "3.0V LVCMOS" |
|
3.0-V LVTTL |
supported device (Arria® V, Cyclone® IV , Cyclone® V , MAX® V) families |
"3.0-V LVTTL", "3.0V LVTTL" |
|
3.0-VPCI |
supported device (Arria® V, and Stratix® IV) families |
"3.0- V PCI" |
|
3.0-VPCI-X |
supported device (Arria® V, and Stratix® IV) families |
"3.0- V PCI- X", "3.0- V PCI X" |
|
3.3-V LVCMOS |
All Intel device families supported by the Intel® Quartus® Prime software |
"3.3-V LVCMOS", "3.3V LVCMOS", "LVCMOS" |
|
3.3-V LVTTL |
All Intel device families supported by the Intel® Quartus® Prime software |
"LVTTL" |
|
3.3-VPCI |
supported device (Arria® V series, MAX® V) families |
"3.3- V PCI" |
|
3.3-VPCI-X |
supported device (Arria® V) families |
"3.3- V PCI- X", "3.3- V PCI X" |
|
3.3-VPCML |
supported device (Cyclone® IV GX) families |
"3.3- V PCML", "PCML", " CML" |
|
3.3-V Schmitt Trigger Input |
MAX® V devices |
"3.3V Schmitt Trigger Input" |
|
Bus LVDS |
supported device (Cyclone® IV devices) |
"Bus LVDS" |
|
Differential I/O standards |
||
|
2.5 V LVDS |
supported device (Arria® V and Cylone V) families |
LVDS |
|
Differential 1.2-V HSTL Class I and II |
supported device (Arria® series, Cyclone®IV, Stratix®IV, and Stratix®V) families |
"Differential 1.2- V HSTL", "Differential 1.2- V HSTL Class I", "Differential 1.2- V HSTL Class II" |
|
Differential 1.2-V HSUL |
supported device (Arria® V, Cyclone® V , and Stratix® V ) families |
"Differential 1.2-V HSUL" |
|
Differential 1.2-V SSTL |
Stratix®V devices |
"Differential 1.2-V SSTL" |
|
Differential 1.25-V SSTL |
supported device (Arria® V, Cyclone® V , and Stratix® V series) families |
"Differential 1.25-V SSTL" |
|
Differential 1.35-V SSTL |
supported device (Arria® V, Cyclone® V , Stratix® V series) families |
"Differential 1.35-V SSTL" |
|
Differential 1.5-V HSTL Class I |
supported device (Arria®series, Cyclone®IV, and Stratix® series) families |
"Differential HSTL", "Differential 1.5- V HSTL", "Differential 1.5- V HSTL Class I" |
|
Differential 1.5-V HSTL Class II |
supported device (Arria® series, Cyclone® IV , Cyclone® V series, Stratix® IV, and Stratix® V ) families |
"Differential HSTL Class II", "Differential 1.5- V HSTL Class II" |
|
Differential 1.5-V SSTL |
supported device (Cyclone® V series and Stratix® V ) families |
"Differential 1.5-V SSTL" |
|
Differential 1.5-V SSTL ClassIand II |
Stratix®V devices |
"Differential 1.5-V SSTL Class I", "Differential 1.5-V SSTL Class II" |
|
Differential 1.8-V HSTL ClassIand II |
supported device (Arria® series, Cyclone® IV , Cyclone® V , and Stratix® series) families |
"Differential 1.8- V HSTL Class I", "Differential 1.8- V HSTL Class II" |
|
Differential 1.8-V SSTL ClassIand II |
supported device (Arria® series, Cyclone® IV , Cyclone® V , and Stratix® IV) families |
"Differential 1.8- V SSTL Class I", "Differential 1.8- V SSTL Class II" |
|
Differential 2.5-V SSTL ClassIand II |
supported device (Arria® V and Stratix® V ) families |
"Differential 2.5- V SSTL Class I" "Differential 2.5- V SSTL Class II" |
|
Differential LVPECL |
supported device (Arria® series, Cyclone® IV , and Stratix® series) families |
"Differential LVPECL" |
|
Differential SSTL-2 ClassI |
supported device (Arria® series, Cyclone® series, and Stratix® IV) families |
"Differential SSTL- 2" |
|
Differential SSTL-2 ClassII |
supported device (Arria® series, Cyclone® IV , and Stratix® IV) families |
"Differential SSTL- 2 Class II" |
|
HCSL |
supported device (Arria® series, Cyclone® IV GX, Stratix® IV, and Stratix® V ) families |
"HCSL" |
|
LVDS |
supported device (Arria® series, Cyclone® series, and Stratix® series) families |
"LVDS" |
|
LVDS_E_1R |
supported device (Stratix® IV) families |
"LVDS_E_1R" |
|
LVDS_E_3R |
supported device (Cyclone® IV , MAX® V, Stratix® IV, and Stratix® V ) families |
"LVDS_E_3R" |
|
LVPECL |
supported device (Arria® V and Cyclone® V ) families |
LVEPCL |
|
mini-LVDS |
supported device (Arria® V, Cyclone® IV , Stratix® IV, and Stratix® V ) families |
"mini-LVDS" |
|
mini-LVDS _E_R |
supported device (Stratix® IV) families |
"mini-LVDS", |
|
mini-LVDS _E_3R |
supported device (Cyclone® IV , Stratix® IV, and Stratix® V ) families |
"mini-LVDS", |
|
RSDS |
supported device (Arria® V series, Cyclone® series, Stratix® IV,and Stratix® V ) families |
"RSDS" |
|
RSDS_E_1R |
supported device (Cyclone® IV , and Stratix® IV) families |
"RSDS_E_1R" |
|
RSDS_E_3R |
supported device (Cyclone® IV , Stratix® IV, and Stratix® V ) families |
"RSDS_E_3R" |
|
Schmitt Trigger Input |
MAX® II devices |
"2.5V Schmitt Trigger Input", "3.3V Schmitt Trigger Input" |
|
SSTL-12 |
Stratix® V devices |
"SSTL-12" |
|
SSTL-125 Class I |
Stratix® V devices |
"SSTL-125" |
|
SSTL-135 Class I |
Stratix® V devices |
"SSTL-135" |
|
SSTL-15 |
Stratix® V deviecs |
"SSTL-15" |
|
SSTL-15 Class I |
supported device (Stratix® IV, and Stratix® V ) families |
"SSTL- 15 Class I" |
|
SSTL-15 Class II |
supported device (Stratix® IV, and Stratix® V ) families |
"SSTL- 15 Class II" |
|
SSTL-18 Class I and II |
supported device (Arria® series, Cyclone® IV , and Stratix® series) families |
"SSTL- 18 Class I", "SSTL- 18 Class II" |
|
SSTL-2 Class I and II |
supported device (Arria® series, Cyclone® series, and Stratix® series) families |
"SSTL- 2 Class I", "SSTL- 2 Class II" |
|
POD12 |
Intel® Arria® 10 devices |
"1.2-V POD |
|
Differential POD12 |
Intel® Arria® 10 devices |
"Differential 1.2-V POD |
|
High Speed Differential |
Intel® Arria® 10 devices |
"High Speed Differential I/O" |
|
PPDS |
Cyclone® IV devices |
"PPDS" |
|
PPDS_E_3R |
Cyclone® IV devices, Intel® MAX® 10 devices |
"PPDS_E_3R" |
|
SLVS |
Cyclone® V devices |
"SLVS" |
|
mini-LVDS_E_1R |
Cyclone® V devices,Arria® V devices |
"mini-LVDS_E_1R" |
|
mini-LVDS_E_3R |
Cyclone® V devices,Arria® V devices |
"mini-LVDS_E_3R |
|
CML |
Intel® Arria® 10 devices |
"CURRENT MODE LOGIC (CML)" |
|
1.5-V Schmitt Trigger Input |
Intel® MAX® 10 devices |
"1.5V Schmitt Trigger Input" |
|
1.8-V Schmitt Trigger Input |
Intel® MAX® 10 devices |
"1.8V Schmitt Trigger Input" |
|
HiSpi |
Cyclone® V devices, Intel® MAX® 10 devices |
"HISPI" |
|
Sub-LVDS |
Cyclone® IV devices, Intel® MAX® 10 devices |
"SUB-LVDS" |
|
TMDS |
Intel® MAX® 10 devices |
TMDS |