VHDL Simulation Files

Allows you to specify files to generate when the VHDL simulation model is generated:

• Output Path—The name of the generated file.
• Source File—Location of the source file.
• Type—The type of file. If a file is an HDL file that can be synthesized, or one of the supported file types, you should specify a matching file type. You can include extra files as generated output that are not synthesized as part of the Quartus^® Prime Standard Edition design; you must specify the file type for these extra files as OTHER.
• Attributes—Allows you to specify that a simulation file should only be created for use in a particular simulator. When an instance of the component is generated, this allows different simulation files to be used for each simulator.

The following options are available in the Verilog Simulation Files table:

• + (Add)— Allows you to add a file to the component.
• - (Remove)— Allows you to remove the component file.
• Copy from Synthesis Files—Allows you to copy the list of synthesis files to be used as the VHDL simulation files. Use this option if your component does not require a custom simulation model and is implemented in VHDL.