Simulation
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Create simulation
model—Creates a Verilog or VHDL
simulation model for the system.
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Allow mixed-language
simulation—Allows a mixed language
simulation model generation. If turned on, if a preferred simulation language is
set, Qsys uses a fileset of the component for the simulation model
generation. When turned off, which is the default, Qsys uses the
selected language for the simulation model.