To setup the simulator environment
- On the Tools menu, click Options and then click EDA Tool Options. Specify the path to
your simulator executable file.
- On the Assignments menu, click Settings.
- In the Category list, select Simulation
under EDA
Tool Settings.
- In the Tool name list, select your supported
simulator.
- If enabled, you can turn on Run gate-level simulation
automatically after compilation.
- In the Format for output
netlist list, select either VHDL or Verilog HDL.
- In the Output directory
box, type or browse to the location where you want output files
saved.
- If you want to map illegal HDL characters, turn on Map illegal HDL characters.
- To filter glitches from the netlist and any corresponding
Standard Delay Format Output File (.sdo) Definition,
turn on Enable glitch filtering.
- If you want to generate a Value Change Dump File (.vcd) Definition file for power
analysis,follow these steps:
- Turn on Generate Value Change Dump (VCD) file script.
- Under Script settings, specify the type of output signals to include in the .vcd script and the name of the test bench instance for which you are performing
the simulation. If you are running your simulation with a test bench selected, the design instance name must be identical to and specified under NativeLink
settings
- To specify less common EDA Netlist Writer
options,follow these
steps:
- Click More EDA
Netlist Writer Settings.
- Type the desired Architecture
name in VHDL output netlist.
- To add the devpor, devclrn, and
devoe signals as input ports in the top-level design
hierarchy in the netlist, turn on Bring out device-wide
set/reset signals as ports.
- To disable setup and hold violation detection in bi-directional
pins, turn on Disable detection of
setup and hold violations detection in input registers of
bi-directional pins.
- To disable writing the entity definition of top-level entity
into the VHDL file, turn on Do Not
Write Top Level VHDL Entity.
- To flatten all buses in the netlist, turn on Flatten buses
into individual nodes.
- To generate a Verilog Output File (.vo) or VHDL Output File (.vho) for a functional simulation, turn
on Generate netlist for functional simulation only.
- To maintain the original design hierarchy in the netlist, turn
on Maintain hierarchy.
- To truncate hierarchical node names to 80 characters or more,
turn on Truncate long hierarchy paths.
- Click OK.
- If you want to specify options for NativeLink automation,
follow these steps:
- To automatically compile a testbench following Quartus® Prime Standard Edition
compilation, turn on Compile test
bench. and specify the Test bench name, Top level
module in test, and
Simulation period.
- To automatically use a script to set up your simulator following Quartus® Prime Standard Edition compilation, turn on Use script to setup simulation and specify the location
of the file that contains the simulation commands.
- To specify less common NativeLink settings, click More NativeLink Settings to choose from these options:
- Generate third-party EDA tool command scripts without running the EDA tool.
- Launch third-party EDA tool in command-line mode.
- Location of user compiled simulation library. Do not use this option to specify the directory for ModelSim-Altera software precompiled libraries or Active-HDL
precompiled libraries.