Preparing for EDA Simulation |
You must compile Altera simulation model files before simulating an Altera design. The Quartus® Prime Standard Edition software includes simulation models for Altera megafunctions, primitives, library of parameterized modules (LPMs), IPFS models, and device family specific models in the <installation path>/eda/sim_lib directory.
You can use any of the following methods to compile Altera simulation models:
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GUI Steps:
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Command-Line Steps:
Type the following at the command line:
quartus_sh --simlib_comp -family <device family> -tool <EDA tools>-tool_path<path to simulation tool executable>-language <verilog/vhdl>-directory <output directory>-log <filename> -cmd_file <output_cmd file>-suppress_messagesThe following table provides information on the available settings with the quartus_sh executable:
Setting |
Required |
Values |
Description |
---|---|---|---|
-family |
Yes |
Any device family all |
The syntax is the device family name in lowercase letters, with no spaces. For example: stratixiigx All device families need to be compiled. |
-tool |
Yes |
activehdl |modelsim |mentor_vhdl_only | ncsim |questasim |rivierapro | vcs |vcsmx |
A supported third-party simulation tool. Note: mentor_vhdl_only represents all mentor simulators such as ModelSim PE, ModelSim SE, and QuestaSim that need to be simulated in VHDL-only mode. Note: No libraries are generated for VCS. Instead, a VCS options file, simlib_comp.vcs, is generated that specifies the library source files. Note: Global libraries are created for Active-HDL, but not for Riviera-PRO. |
-tool_path |
No |
User-specified |
Path to simulation tool executable. |
-language |
Yes |
verilog | vhdl |
HDL language used for the simulation. |
-directory |
No |
User specified | current ( ./ ) |
Specifies an output directory for the compiled libraries. The default is the directory where you run the quartus_sh executable. Libraries are compiled into a single directory (< directory >/verilog_libs or < directory >/vhdl_libs) containing subdirectories for each of the compiled libraries. The subdirectory names for Verilog HDL libraries always contain the _ver suffix; whereas, the VHDL library directories have no suffix. For example: The Verilog HDL version of the altera_mf library is:<directory>/verilog_libs/altera_mf_ver and the VHDL version is:<directory>/vhdl_libs/altera_mf. |
-log |
No |
<log file name> |
Specifies the file in which to store all messages issued during compilation that were not suppressed with-suppress_messages. If this setting is not specified then a log file is not created. |
-cmd_file |
No |
<output_cmd file> |
The output file containing simulator commands used to compile the specified libraries. |
-gen_only |
No |
Specifies that only the tool command script should be generated (i.e., the simulator should not be invoked to compile the libraries). If this option is specified, -cmd_file should also be specified. Note: The library setup files for vcsmx and ncsim will be created even when this option is on. |
|
-suppress_messages |
No |
Specifies whether or not to suppress simulation-tool specific information and warning messages issued during compilation. This setting does not apply to tool-specific error messages. Messages that are suppressed do not appear in a log file, if one is created with the-log<filename> option. |
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