CTRLR0
|
0x0
|
32
|
RW
|
0x00070000
|
Control Register 0
|
SSIENR
|
0x8
|
32
|
RW
|
0x00000000
|
SSI Enable Register
|
MWCR
|
0xC
|
32
|
RW
|
0x00000000
|
Microwire Control Register
|
TXFTLR
|
0x18
|
32
|
RW
|
0x00000000
|
Transmit FIFO Threshold Level
|
RXFTLR
|
0x1C
|
32
|
RW
|
0x00000000
|
Receive FIFO Threshold Level
|
TXFLR
|
0x20
|
32
|
RO
|
0x00000000
|
Transmit FIFO Level Register
|
RXFLR
|
0x24
|
32
|
RO
|
0x00000000
|
Receive FIFO Level Register
|
SR
|
0x28
|
32
|
RO
|
0x00000006
|
Status Register
|
IMR
|
0x2C
|
32
|
RW
|
0x0000001F
|
Interrupt Mask Register
|
ISR
|
0x30
|
32
|
RO
|
0x00000000
|
Interrupt Status Register
|
RISR
|
0x34
|
32
|
RO
|
0x00000000
|
Raw Interrupt Status Register
|
TXOICR
|
0x38
|
32
|
RO
|
0x00000000
|
Transmit FIFO Overflow Interrupt Clear Register Register
|
RXOICR
|
0x3C
|
32
|
RO
|
0x00000000
|
Receive FIFO Overflow Interrupt Clear Register
|
RXUICR
|
0x40
|
32
|
RO
|
0x00000000
|
Receive FIFO Underflow Interrupt Clear Register
|
MSTICR
|
0x44
|
32
|
RO
|
0x00000000
|
Multi-Master Interrupt Clear Register
|
ICR
|
0x48
|
32
|
RO
|
0x00000000
|
Interrupt Clear Register
|
DMACR
|
0x4C
|
32
|
RW
|
0x00000000
|
DMA Control Register
|
DMATDLR
|
0x50
|
32
|
RW
|
0x00000000
|
DMA Transmit Data Level
|
DMARDLR
|
0x54
|
32
|
RW
|
0x00000000
|
DMA Receive Data Level
|
IDR
|
0x58
|
32
|
RO
|
0x05510005
|
Identification Register
|
SSI_VERSION_ID
|
0x5C
|
32
|
RO
|
0x3430302A
|
coreKit Version ID Register
|
DR0
|
0x60
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR1
|
0x64
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR2
|
0x68
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR3
|
0x6C
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR4
|
0x70
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR5
|
0x74
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR6
|
0x78
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR7
|
0x7C
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR8
|
0x80
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR9
|
0x84
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR10
|
0x88
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR11
|
0x8C
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR12
|
0x90
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR13
|
0x94
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR14
|
0x98
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR15
|
0x9C
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR16
|
0xA0
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR17
|
0xA4
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR18
|
0xA8
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR19
|
0xAC
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR20
|
0xB0
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR21
|
0xB4
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR22
|
0xB8
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR23
|
0xBC
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR24
|
0xC0
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR25
|
0xC4
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR26
|
0xC8
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR27
|
0xCC
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR28
|
0xD0
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR29
|
0xD4
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR30
|
0xD8
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR31
|
0xDC
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR32
|
0xE0
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR33
|
0xE4
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR34
|
0xE8
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
DR35
|
0xEC
|
32
|
RW
|
0x00000000
|
DW_apb_ssi Data Register
|
RSVD_1
|
0xF8
|
32
|
RO
|
0x00000000
|
RSVD_1 - Reserved address location
|
RSVD_2
|
0xFC
|
32
|
RO
|
0x00000000
|
RSVD_2 - Reserved address location
|