noc_ccu_ios_emac_tbu_m_I_main_TransactionStatFilter Summary
Base Address: 0xFFD24400
Register Address Offset |
Bit Fields | |||||||||||||||
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i_noc_ccu_ios_emac_tbu_m_I_main_TransactionStatFilter | ||||||||||||||||
emac_tbu_m_I_main_TransactionStatFilter_Id_CoreId 0x0 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CORECHECKSUM RO 0xC050C0 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CORECHECKSUM RO 0xC050C0 |
CORETYPEID RO 0x9 |
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emac_tbu_m_I_main_TransactionStatFilter_Id_RevisionId 0x4 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FLEXNOCID RO 0x148 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
FLEXNOCID RO 0x148 |
USERID RO 0x0 |
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emac_tbu_m_I_main_TransactionStatFilter_Mode 0x8 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Reserved |
MODE RW 0x0 |
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emac_tbu_m_I_main_TransactionStatFilter_AddrBase_Low 0xC 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADDRBASE_LOW RW 0x0 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ADDRBASE_LOW RW 0x0 |
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emac_tbu_m_I_main_TransactionStatFilter_AddrBase_High 0x10 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Reserved |
ADDRBASE_HIGH RW 0x0 |
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emac_tbu_m_I_main_TransactionStatFilter_AddrWindowSize 0x14 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Reserved |
ADDRWINDOWSIZE RW 0x0 |
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emac_tbu_m_I_main_TransactionStatFilter_Opcode 0x20 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Reserved |
WREN RW 0x0 |
RDEN RW 0x0 |
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emac_tbu_m_I_main_TransactionStatFilter_UserBase 0x24 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
USERBASE RW 0x0 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
USERBASE RW 0x0 |
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emac_tbu_m_I_main_TransactionStatFilter_UserMask 0x28 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
USERMASK RW 0x0 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
USERMASK RW 0x0 |
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emac_tbu_m_I_main_TransactionStatFilter_SecurityBase 0x2C 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Reserved |
SECURITYBASE RW 0x0 |
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emac_tbu_m_I_main_TransactionStatFilter_SecurityMask 0x30 32-bit |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Reserved |
SECURITYMASK RW 0x0 |