emac_tbu_m_I_main_TransactionStatFilter_SecurityMask

         EMAC TBU Transaction Statistics Filter Security Mask Register
      
Module Instance Base Address Register Address
i_noc_ccu_ios_emac_tbu_m_I_main_TransactionStatFilter 0xFFD24400 0xFFD24430

Size: 32

Offset: 0x30

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

SECURITYMASK

RW 0x0

emac_tbu_m_I_main_TransactionStatFilter_SecurityMask Fields

Bit Name Description Access Reset
1:0 SECURITYMASK
This register contains the Security mask used to filter requests.
RW 0x0