noc_fw_ddr_fpga2sdram_inst_1_ddr_scr Summary

DDR Security Control Registers (SCR)

Base Address: 0xF8020300

Register Address Offset	Bit Fields
`soc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr`
`enable` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`region3enable` `RW 0x0`	`region2enable` `RW 0x0`	`region1enable` `RW 0x0`	`region0enable` `RW 0x0`
`enable_set` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`region3enable` `WO 0x0`	`region2enable` `WO 0x0`	`region1enable` `WO 0x0`	`region0enable` `WO 0x0`
`enable_clear` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`region3enable` `WO 0x0`	`region2enable` `WO 0x0`	`region1enable` `WO 0x0`	`region0enable` `WO 0x0`
`region0addr_base` `0x10` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`high` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`low` `RO 0x0`
`region0addr_baseext` `0x14` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`low` `RW 0x0`
`region0addr_limit` `0x18` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`high` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`low` `RO 0xFFFF`
`region0addr_limitext` `0x1C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`low` `RW 0x0`
`region1addr_base` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`high` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`low` `RO 0x0`
`region1addr_baseext` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`low` `RW 0x0`
`region1addr_limit` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`high` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`low` `RO 0xFFFF`
`region1addr_limitext` `0x2C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`low` `RW 0x0`
`region2addr_base` `0x30` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`high` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`low` `RO 0x0`
`region2addr_baseext` `0x34` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`low` `RW 0x0`
`region2addr_limit` `0x38` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`high` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`low` `RO 0xFFFF`
`region2addr_limitext` `0x3C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`low` `RW 0x0`
`region3addr_base` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`high` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`low` `RO 0x0`
`region3addr_baseext` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`low` `RW 0x0`
`region3addr_limit` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`high` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`low` `RO 0xFFFF`
`region3addr_limitext` `0x4C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`low` `RW 0x0`