region0addr_limitext

         limit extended definition for Region 0

Module Instance	Base Address	Register Address
`soc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr`	`0xF8020300`	`0xF802031C`

Size: 32

Offset: 0x1C

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`											`low` `RW 0x0`

region0addr_limitext Fields

Bit	Name	Description	Access	Reset
4:0	`low`	defines the 5 bit LSB of the limit extended address field.	`RW`	`0x0`