NAND_dma Summary

Base Address: 0xFFB80700

Register Address Offset	Bit Fields
`i_nand_dma`
`dma_enable` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`flag` `RW 0x0`
`dma_intr` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`cmddma_idle` `RW 0x0`	`Reserved`	`desc_comp_channel3` `RW 0x0`	`desc_comp_channel2` `RW 0x0`	`desc_comp_channel1` `RW 0x0`	`desc_comp_channel0` `RW 0x0`	`target_error` `RW 0x0`
`dma_intr_en` `0x30` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`cmddma_idle` `RW 0x0`	`Reserved`	`desc_comp_channel3` `RW 0x0`	`desc_comp_channel2` `RW 0x0`	`desc_comp_channel1` `RW 0x0`	`desc_comp_channel0` `RW 0x0`	`target_error` `RW 0x0`
`target_err_addr_lo` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`target_err_addr_hi` `0x50` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`flash_burst_length` `0x70` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`polling_sync_counter_value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`polling_sync_counter_value` `RW 0x0`								`Reserved`			`continous_burst` `RW 0x0`	`Reserved`		`value` `RW 0x1`
`chip_interleave_enable_and_allow_int_reads` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cmd_dma_error_enable` `RW 0x1`	`Reserved`			`allow_int_reads_within_luns` `RW 0x1`	`Reserved`			`chip_interleave_enable` `RW 0x0`
`no_of_blocks_per_lun` `0xA0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`			`issue_read_before_sync` `RW 0x0`	`Reserved`			`update_sync_before_prog_comp` `RW 0x0`	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`value` `RW 0xF`
`lun_status_cmd` `0xB0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x7878`
`chnl_active` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`channel3` `RO 0x0`	`channel2` `RO 0x0`	`channel1` `RO 0x0`	`channel0` `RO 0x0`
`cmd_dma_channel_error` `0xC0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`channel3` `RW 0x0`	`channel2` `RW 0x0`	`channel1` `RW 0x0`	`channel0` `RW 0x0`
`cmd_dma_channel_error_en` `0xD0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`channel3` `RW 0x0`	`channel2` `RW 0x0`	`channel1` `RW 0x0`	`channel0` `RW 0x0`
`rescan_buffer_flag` `0x90` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`flag` `RW 0x0`