flash_burst_length
Module Instance Base Address Register Address
i_nand_dma 0xFFB80700 0xFFB80770

Size: 32

Offset: 0x70

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

polling_sync_counter_value

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

polling_sync_counter_value

RW 0x0

Reserved

continous_burst

RW 0x0

Reserved

value

RW 0x1

flash_burst_length Fields

Bit Name Description Access Reset
31:8 polling_sync_counter_value 
Number of cycles CMDDMA channel has to wait before polling the SYNC Pointer again.
                      If this counter value is 0, no polling is done.
RW 0x0
4 continous_burst 
When this bit is set, the Data DMA will burst the entire page from/to the
                     flash device. Please make sure that the host system can provide/sink data 
                     at a fast pace to avoid unnecessary pausing of data on the device interface.
 RW 0x0
1:0 value 
Sets the burst used by data dma for transferring data to/from flash device.
                      This burst length is different and is larger than the burst length on the
                      host bus so that larger amount of data can be transferred to/from device,
                      descreasing controller data transfer overhead in the process.
                      00 - 64 bytes, 01 - 128 bytes, 10 - 256 bytes, 11 - 512 bytes.
                      The host burst size multiplied by the number of outstanding requests on the
                      host side should be greater than equal to this value. If not, the device side
                      burst length will be equal to host side burst length.
RW 0x1