sdm_NAND_e_ecc Address Map

Module Instance Base Address End Address
sdm_ecc_nand_e_ecc_registerBlock 0xFFA21800 0xFFA21BFF
Register Offset Width Access Reset Value Description
IP_REV_ID 0x0 32 RO 0x00000000 
IP slicon revision ID
CTRL 0x8 32 RW 0x00000002 
ECC Control Register
INITSTAT 0xC 32 RW 0x00000000 
Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB
ERRINTEN 0x10 32 RW 0x00000000 
Error Interrupt enable
ERRINTENS 0x14 32 RW 0x00000000 
Error interrupt set
ERRINTENR 0x18 32 RW 0x00000000 
Error Interrupt reset
INTMODE 0x1C 32 RW 0x00000000 
Interrupt modes of ECC RAM system
INTSTAT 0x20 32 RW 0x00000000 
This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled, serr_req signal will be asserted.
INTTEST 0x24 32 RW 0x00000000 
This bits is used to test interrupt from ECC RAM to GIC
MODSTAT 0x28 32 RW 0x00000000 
Mode status flag
DERRADDRA 0x2C 32 RO 0x00000000 
This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits.
SERRADDRA 0x30 32 RO 0x00000000 
This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits.
DERRADDRB 0x34 32 RO 0x00000000 
This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits.
SERRADDRB 0x38 32 RO 0x00000000 
This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits.
SERRCNTREG 0x3C 32 RW 0x00000000 
Maximum counter value for single-bit error interrupt
ECC_Addrbus 0x40 32 RW 0x00000000 
MSB bit of address is determined by ADR.
ECC_RData0bus 0x44 32 RO 0x00000000 
Data will be read to this register field.
ECC_RData1bus 0x48 32 RO 0x00000000 
Data will be read to this register field.
ECC_RData2bus 0x4C 32 RO 0x00000000 
Data will be read to this register field.
ECC_RData3bus 0x50 32 RO 0x00000000 
Data will be read to this register field.
ECC_WData0bus 0x54 32 WO 0x00000000 
Data from the register will be written to the RAM.
ECC_WData1bus 0x58 32 WO 0x00000000 
Data from the register will be written to the RAM.
ECC_WData2bus 0x5C 32 WO 0x00000000 
Data from the register will be written to the RAM.
ECC_WData3bus 0x60 32 WO 0x00000000 
Data from the register will be written to the RAM.
ECC_RDataecc0bus 0x64 32 RO 0x00000000 
The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.
ECC_RDataecc1bus 0x68 32 RO 0x00000000 
The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.
ECC_WDataecc0bus 0x6C 32 WO 0x00000000 
The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.
ECC_WDataecc1bus 0x70 32 WO 0x00000000 
The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.
ECC_dbytectrl 0x74 32 RW 0x00000000 
Max number of implemented byte enabled is DAT/8
ECC_accctrl 0x78 32 RW 0x00000000 
These bits determine which byte of data/ecc to write to RAM.
ECC_startacc 0x7C 32 RW 0x00000000 
These bits determine which byte of data/ecc to write to RAM.
ECC_wdctrl 0x80 32 RW 0x00000000 
Bits to Enable/Disable Watch Dog Timer
SERRLKUPA0 0x90 32 RW 0x00000000 
Single-bit error address in LOOKUP TABLE for PORTA.
Valid flag bit. Valid bit indicates if the address in this register is current or stale.

IF IP is having a single decoder, VALID8 will be used
IF IP is having multiple decoder, The lowest decoder will be represented on VALID1 and the next will on VALID2.
It increases onward to VALID8.
SERRLKUPB0 0xD0 32 RW 0x00000000 
Single-bit error address in LOOKUP TABLE for PORTB.
Valid flag bit. Valid bit indicates if the address in this register is current or stale.

IF IP is having a single decoder, VALID8 will be used
IF IP is having multiple decoder, The lowest decoder will be represented on VALID1 and the next will on VALID2.
It increases onward to VALID8.
IP_REV_ID2 0x4 32 RO 0x00000000 
IP memory configuration
ECC_DECODERSTAT 0x84 32 RW 0x00000000 
Individual decoder flags for single and double bits errors.
Each decoder flags used represent one decoder in the design.