Reset Manager Module Summary

Registers in the Reset Manager module

Base Address: 0xFFD05000

Register Address Offset	Bit Fields
`stat` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`			`etrstalltimeout` `RW 0x0`	`fpgahstimeout` `RW 0x0`	`scanhstimeout` `RW 0x0`	`fpgamgrhstimeout` `RW 0x0`	`sdrselfreftimeout` `RW 0x0`	`Reserved`				`cdbgreqrst` `RW 0x0`	`fpgadbgrst` `RW 0x0`	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`l4wd1rst` `RW 0x0`	`l4wd0rst` `RW 0x0`	`mpuwd1rst` `RW 0x0`	`mpuwd0rst` `RW 0x0`	`Reserved`	`swwarmrst` `RW 0x0`	`fpgawarmrst` `RW 0x0`	`nrstpinrst` `RW 0x0`	`Reserved`			`swcoldrst` `RW 0x0`	`configiocoldrst` `RW 0x0`	`fpgacoldrst` `RW 0x0`	`nporpinrst` `RW 0x0`	`porvoltrst` `RW 0x0`
`ctrl` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`								`etrstallwarmrst` `RW 0x0`	`etrstallack` `RO 0x0`	`etrstallreq` `RW 0x0`	`etrstallen` `RW 0x1`	`Reserved`	`fpgahsack` `RO 0x0`	`fpgahsreq` `RW 0x0`	`fpgahsen` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`	`scanmgrhsack` `RO 0x0`	`scanmgrhsreq` `RW 0x0`	`scanmgrhsen` `RW 0x0`	`Reserved`	`fpgamgrhsack` `RO 0x0`	`fpgamgrhsreq` `RW 0x0`	`fpgamgrhsen` `RW 0x0`	`Reserved`	`sdrselfreqack` `RO 0x0`	`sdrselfrefreq` `RW 0x0`	`sdrselfrefen` `RW 0x0`	`Reserved`		`swwarmrstreq` `RW 0x0`	`swcoldrstreq` `RW 0x0`
`counts` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`				`nrstcnt` `RW 0x800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`nrstcnt` `RW 0x800`								`warmrstcycles` `RW 0x80`
`mpumodrst` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`l2` `RW 0x0`	`scuper` `RW 0x0`	`wds` `RW 0x0`	`cpu1` `RW 0x1`	`cpu0` `RW 0x0`
`permodrst` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`		`sdr` `RW 0x1`	`dma` `RW 0x1`	`gpio2` `RW 0x1`	`gpio1` `RW 0x1`	`gpio0` `RW 0x1`	`Reserved`	`Reserved`	`sdmmc` `RW 0x1`	`spis1` `RW 0x1`	`spis0` `RW 0x1`	`spim1` `RW 0x1`	`spim0` `RW 0x1`	`uart1` `RW 0x1`	`uart0` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`i2c3` `RW 0x1`	`i2c2` `RW 0x1`	`i2c1` `RW 0x1`	`i2c0` `RW 0x1`	`sptimer1` `RW 0x1`	`sptimer0` `RW 0x1`	`osc1timer1` `RW 0x1`	`osc1timer0` `RW 0x1`	`l4wd1` `RW 0x1`	`l4wd0` `RW 0x1`	`qspi` `RW 0x1`	`nand` `RW 0x1`	`usb1` `RW 0x1`	`usb0` `RW 0x1`	`emac1` `RW 0x1`	`emac0` `RW 0x1`
`per2modrst` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`dmaif7` `RW 0x1`	`dmaif6` `RW 0x1`	`dmaif5` `RW 0x1`	`dmaif4` `RW 0x1`	`dmaif3` `RW 0x1`	`dmaif2` `RW 0x1`	`dmaif1` `RW 0x1`	`dmaif0` `RW 0x1`
`brgmodrst` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`fpga2hps` `RW 0x1`	`lwhps2fpga` `RW 0x1`	`hps2fpga` `RW 0x1`
`miscmodrst` `0x20`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`															`sdrcold` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`tapcold` `RW 0x0`	`dbg` `RW 0x0`	`sysdbg` `RW 0x0`	`frzctrlcold` `RW 0x0`	`scanmgr` `RW 0x0`	`clkmgrcold` `RW 0x0`	`timestampcold` `RW 0x0`	`nrstpin` `RW 0x0`	`s2fcold` `RW 0x0`	`s2f` `RW 0x0`	`acpidmap` `RW 0x0`	`fpgamgr` `RW 0x0`	`sysmgrcold` `RW 0x0`	`sysmgr` `RW 0x0`	`ocram` `RW 0x0`	`rom` `RW 0x0`
`tstscratch` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`field0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`field0` `RW 0x0`