noc_mpu_emac0_m_I_main_TransactionStatFilter Address Map

Module Instance	Base Address	End Address
`i_noc_mpu_m0_emac0_m_I_main_TransactionStatFilter`	`0xFFD17080`	`0xFFD9FFFF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`emac0_m_I_main_TransactionStatFilter_Id_CoreId`	`0x0`	`32`	`RO`	`0xC284D309`
`emac0_m_I_main_TransactionStatFilter_Id_RevisionId`	`0x4`	`32`	`RO`	`0x129FF00`
`emac0_m_I_main_TransactionStatFilter_Mode`	`0x8`	`32`	`RW`	`0x0`
`emac0_m_I_main_TransactionStatFilter_AddrBase_Low`	`0xC`	`32`	`RW`	`0x0`
`emac0_m_I_main_TransactionStatFilter_AddrBase_High`	`0x10`	`32`	`RW`	`0x0`
`emac0_m_I_main_TransactionStatFilter_AddrWindowSize`	`0x14`	`32`	`RW`	`0x0`
`emac0_m_I_main_TransactionStatFilter_Opcode`	`0x20`	`32`	`RW`	`0x0`	This register selects candidate packets based on packet opcodes. (0 disables the filter):
`emac0_m_I_main_TransactionStatFilter_UserBase`	`0x24`	`32`	`RW`	`0x0`
`emac0_m_I_main_TransactionStatFilter_UserMask`	`0x28`	`32`	`RW`	`0x0`
`emac0_m_I_main_TransactionStatFilter_SecurityBase`	`0x2C`	`32`	`RW`	`0x0`
`emac0_m_I_main_TransactionStatFilter_SecurityMask`	`0x30`	`32`	`RW`	`0x0`