io48_pin_mux_fpga_interface_grp Address Map
This register set is used to select whether peripheral signals are mapped to the HPS or FPGA pins. This selection is available for the EMACs, I2Cs, NAND, QSPI, SD/MMC, SPIs and UARTs.
| Module Instance | Base Address | End Address |
|---|---|---|
| i_io48_pin_mux_fpga_interface_grp | 0xFFD07400 | 0xFFD10FFF |
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Register | Offset | Width | Access | Reset Value | Description |
|---|---|---|---|---|---|
| pinmux_emac0_usefpga | 0x0 | 32 | RW | 0x0 | Select source for EMAC0 signals (HPS Pins or FPGA Interface) |
| pinmux_emac1_usefpga | 0x4 | 32 | RW | 0x0 | Select source for EMAC1 signals (HPS Pins or FPGA Interface) |
| pinmux_emac2_usefpga | 0x8 | 32 | RW | 0x0 | Select source for EMAC2 signals (HPS Pins or FPGA Interface) |
| pinmux_i2c0_usefpga | 0xC | 32 | RW | 0x0 | Select source for I2C0 signals (HPS Pins or FPGA Interface) |
| pinmux_i2c1_usefpga | 0x10 | 32 | RW | 0x0 | Select source for I2C1 signals (HPS Pins or FPGA Interface) |
| pinmux_i2c_emac0_usefpga | 0x14 | 32 | RW | 0x0 | Select source for I2C_EMAC0 signals (HPS Pins or FPGA Interface) |
| pinmux_i2c_emac1_usefpga | 0x18 | 32 | RW | 0x0 | Select source for I2C_EMAC1 signals (HPS Pins or FPGA Interface) |
| pinmux_i2c_emac2_usefpga | 0x1C | 32 | RW | 0x0 | Select source for I2C_EMAC2 signals (HPS Pins or FPGA Interface) |
| pinmux_nand_usefpga | 0x20 | 32 | RW | 0x0 | Select source for NAND signals (HPS Pins or FPGA Interface) |
| pinmux_qspi_usefpga | 0x24 | 32 | RW | 0x0 | Select source for QSPI signals (HPS Pins or FPGA Interface) |
| pinmux_sdmmc_usefpga | 0x28 | 32 | RW | 0x0 | Select source for SDMMC signals (HPS Pins or FPGA Interface) |
| pinmux_spim0_usefpga | 0x2C | 32 | RW | 0x0 | Select source for SPIM0 signals (HPS Pins or FPGA Interface) |
| pinmux_spim1_usefpga | 0x30 | 32 | RW | 0x0 | Select source for SPIM1 signals (HPS Pins or FPGA Interface) |
| pinmux_spis0_usefpga | 0x34 | 32 | RW | 0x0 | Select source for SPIS0 signals (HPS Pins or FPGA Interface) |
| pinmux_spis1_usefpga | 0x38 | 32 | RW | 0x0 | Select source for SPIS1 signals (HPS Pins or FPGA Interface) |
| pinmux_uart0_usefpga | 0x3C | 32 | RW | 0x0 | Select source for UART0 signals (HPS Pins or FPGA Interface) |
| pinmux_uart1_usefpga | 0x40 | 32 | RW | 0x0 | Select source for UART1 signals (HPS Pins or FPGA Interface) |