pinmux_spim0_usefpga

         Selection between HPS Pin and FPGA Interface for SPIM0 signals
Only reset by a cold reset (ignores warm reset).
NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.

Module Instance	Base Address	Register Address
`i_io48_pin_mux_fpga_interface_grp`	`0xFFD07400`	`0xFFD0742C`

Offset: 0x2C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`sel` `RW 0x0`

pinmux_spim0_usefpga Fields

Bit	Name	Description	Access	Reset
31:1	`Reserved`	Reserved	`RO`	`0x0`
0	`sel`	Select connection for SPIM0. 0 : SPIM0 uses HPS IO Pins. 1 : SPIM0 uses the FPGA Inteface.	`RW`	`0x0`