qspi_ecc Address Map

Module Instance	Base Address	End Address
`ecc_qspi_ecc_registerBlock`	`0xFF8C8400`	`0xFF8C87FF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`IP_REV_ID`	`0x0`	`32`	`RO`	`0x0`
`CTRL`	`0x8`	`32`	`RW`	`0x0`	ECC Control Register
`INITSTAT`	`0xC`	`32`	`RW`	`0x0`	This bit is used to set the initialize the memory and ecc to a known value
`ERRINTEN`	`0x10`	`32`	`RW`	`0x0`	Error Interrupt enable
`ERRINTENS`	`0x14`	`32`	`RW`	`0x0`	Error Interrupt set
`ERRINTENR`	`0x18`	`32`	`RW`	`0x0`	Error Interrupt reset.
`INTMODE`	`0x1C`	`32`	`RW`	`0x0`	Reads reflect SERRINTEN.
`INTSTAT`	`0x20`	`32`	`RW`	`0x0`	This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled, serr_req signal will be asserted.
`INTTEST`	`0x24`	`32`	`RW`	`0x0`	This bits is used to test interrupt from ECC RAM to GIC
`MODSTAT`	`0x28`	`32`	`RW`	`0x0`	Counter feature status flag
`DERRADDRA`	`0x2C`	`32`	`RO`	`0x0`	This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits.
`SERRADDRA`	`0x30`	`32`	`RO`	`0x0`	This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits.
`SERRCNTREG`	`0x3C`	`32`	`RW`	`0x0`	Maximum counter value for single-bit error interrupt
`ECC_Addrbus`	`0x40`	`32`	`RW`	`0x0`	MSB bit of address is determined by ADR.
`ECC_RData0bus`	`0x44`	`32`	`RO`	`0x0`	Data will be read to this register field.
`ECC_RData1bus`	`0x48`	`32`	`RO`	`0x0`	Data will be read to this register field.
`ECC_RData2bus`	`0x4C`	`32`	`RO`	`0x0`	Data will be read to this register field.
`ECC_RData3bus`	`0x50`	`32`	`RO`	`0x0`	Data will be read to this register field.
`ECC_WData0bus`	`0x54`	`32`	`WO`	`0x0`	Data from the register will be written to the RAM.
`ECC_WData1bus`	`0x58`	`32`	`WO`	`0x0`	Data from the register will be written to the RAM.
`ECC_WData2bus`	`0x5C`	`32`	`WO`	`0x0`	Data from the register will be written to the RAM.
`ECC_WData3bus`	`0x60`	`32`	`WO`	`0x0`	Data from the register will be written to the RAM.
`ECC_RDataecc0bus`	`0x64`	`32`	`RO`	`0x0`	The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.
`ECC_RDataecc1bus`	`0x68`	`32`	`RO`	`0x0`	The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.
`ECC_WDataecc0bus`	`0x6C`	`32`	`WO`	`0x0`	The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.
`ECC_WDataecc1bus`	`0x70`	`32`	`WO`	`0x0`	The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.
`ECC_dbytectrl`	`0x74`	`32`	`RW`	`0x0`	Max number of implemented byte enabled is DAT/8
`ECC_accctrl`	`0x78`	`32`	`RW`	`0x0`	These bits determine which byte of data/ecc to write to RAM.
`ECC_startacc`	`0x7C`	`32`	`RW`	`0x0`	These bits determine which byte of data/ecc to write to RAM.
`ECC_wdctrl`	`0x80`	`32`	`RW`	`0x0`	Bits to Enable/Disable Watch Dog Timer
`SERRLKUPA0`	`0x90`	`32`	`RW`	`0x0`	Single-bit error address in LOOKUP TABLE for PORTA.