GIC_CPUif Address Map

Memory map for the GIC CPU interface blocks. Contains all registers with the GICC prefix. Note: The CPU interface block for each CPU is separate. Note: Some registers are security-banked or banked per-CPU. For details of these registers, please refer to the Arm https://developer.arm.com/docs/ddi0471/b Corelink GIC-400 Generic Interrupt Controller Technical Reference Manual.
Module Instance Base Address End Address
i_gic_wrapper_CPUif 0xFFFC2000 0xFFFC3FFF
Register Offset Width Access Reset Value Description
GICC_CTLR 0x0 32 RW 0x00000000
CPU Interface Control Register
GICC_PMR 0x4 32 RW 0x00000000
Interrupt Priority Mask Register
GICC_BPR 0x8 32 RW 0x00000002
Binary Point Register
GICC_IAR 0xC 32 RO 0x000003FF
Interrupt Acknowledge Register
GICC_EOIR 0x10 32 WO 0x0
End of Interrupt Register
GICC_RPR 0x14 32 RO 0x000000FF
Running Priority Register
GICC_HPPIR 0x18 32 RO 0x000003FF
Highest Priority Pending Interrupt Register
GICC_ABPR 0x1C 32 RW 0x00000003
Aliased Binary Point Register
GICC_AIAR 0x20 32 RO 0x000003FF
Aliased Interrupt Acknowledge Register
GICC_AEOIR 0x24 32 WO 0x0
Aliased End of Interrupt Register
GICC_AHPPIR 0x28 32 RO 0x000003FF
Aliased Highest Priority Pending Interrupt Register
GICC_APR0 0xD0 32 RW 0x00000000
Active Priority Register
GICC_NSAPR0 0xE0 32 RW 0x00000000
Non-Secure Active Priority Register
GICC_IIDR 0xFC 32 RO 0x0202143B
CPU Interface Identification Register
GICC_DIR 0x1000 32 WO 0x0
Deactivate Interrupt Register