Intel_grp Summary

Contains registers with settings for Altera internal use.

Base Address: 0xFFD100D0

Register

Address Offset

 Bit Fields
i_clk_mgr_alteragrp

jtag

0x0

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

rst

RW 0x1

id

RW 0x80

emacactr

0x4

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x1

emacbctr

0x8

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x3

emacptpctr

0xC

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x1

gpiodbctr

0x10

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x0

sdmmcctr

0x14

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x0

s2fuser0ctr

0x18

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x0

s2fuser1ctr

0x1C

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x0

psirefctr

0x20

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

src

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x0

extcntrst

0x24

32-bit

 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

psirefcntrst

RW 0x1

s2fuser1cntrst

RW 0x1

s2fuser0cntrst

RW 0x1

sdmmccntrst

RW 0x1

gpiodbcntrst

RW 0x1

emacptpcntrst

RW 0x1

emacbcntrst

RW 0x1

emacacntrst

RW 0x1