extcntrst 

         Used to hold associated pingpong counter in reset while PLL and 5:1 mux configuration is changed.
1'h1 = PingPong Counter in reset
1'h0 = PingPong Counter not in reset
Module Instance Base Address Register Address
i_clk_mgr_alteragrp 0xFFD100D0 0xFFD100F4

Size: 32

Offset: 0x24

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

psirefcntrst

RW 0x1

s2fuser1cntrst

RW 0x1

s2fuser0cntrst

RW 0x1

sdmmccntrst

RW 0x1

gpiodbcntrst

RW 0x1

emacptpcntrst

RW 0x1

emacbcntrst

RW 0x1

emacacntrst

RW 0x1

extcntrst Fields

Bit Name Description Access Reset
7 psirefcntrst 
This bit holds the associated psi_ref external pingpong counter in reset while PLL and 5:1 mux configuration is changed.
0x1 = pingpong counter is in reset
0x0 = pingpong counter is not in reset
 RW 0x1
6 s2fuser1cntrst 
This bit holds the associated s2f_user1 external pingpong counter in reset while PLL and 5:1 mux configuration is changed.
0x1 = pingpong counter is in reset
0x0 = pingpong counter is not in reset
 RW 0x1
5 s2fuser0cntrst 
This bit holds the associated s2f_user0 external pingpong counter in reset while PLL and 5:1 mux configuration is changed.
0x1 = pingpong counter is in reset
0x0 = pingpong counter is not in reset
 RW 0x1
4 sdmmccntrst 
This bit holds the associated sdmmc external pingpong counter in reset while PLL and 5:1 mux configuration is changed.
0x1 = pingpong counter is in reset
0x0 = pingpong counter is not in reset
 RW 0x1
3 gpiodbcntrst 
This bit holds the associated gpio_db external pingpong counter in reset while PLL and 5:1 mux configuration is changed.
0x1 = pingpong counter is in reset
0x0 = pingpong counter is not in reset
 RW 0x1
2 emacptpcntrst 
This bit holds the associated emac_ptp external pingpong counter in reset while PLL and 5:1 mux configuration is changed.
0x1 = pingpong counter is in reset
0x0 = pingpong counter is not in reset
 RW 0x1
1 emacbcntrst 
This bit holds the associated emacb external pingpong counter in reset while PLL and 5:1 mux configuration is changed.
0x1 = pingpong counter is in reset
0x0 = pingpong counter is not in reset
 RW 0x1
0 emacacntrst 
This bit holds the associated emaca external pingpong counter in reset while PLL and 5:1 mux configuration is changed.
0x1 = pingpong counter is in reset
0x0 = pingpong counter is not in reset
 RW 0x1