Timer_SP Summary

DW_apb_timers address block

Module Instance	Base Address
`i_timer_sp_0_DW_apb_timers_addr_block`	`0xFFC03000`
`i_timer_sp_1_DW_apb_timers_addr_block`	`0xFFC03100`

Register Address Offset	Bit Fields
`i_timer_sp_0_DW_apb_timers_addr_block`
`TIMER1LOADCOUNT` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIMER1LOADCOUNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIMER1LOADCOUNT` `RW 0x0`
`TIMER1CURRENTVAL` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIMER1CURRENTVAL` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIMER1CURRENTVAL` `RO 0x0`
`TIMER1CONTROLREG` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`TIMER_INTERRUPT_MASK` `RW 0x0`	`TIMER_MODE` `RW 0x0`	`TIMER_ENABLE` `RW 0x0`
`TIMER1EOI` `0xC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMER1EOI` `RO 0x0`
`TIMER1INTSTAT` `0x10` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMER1INTSTAT` `RO 0x0`
`TIMERSINTSTAT` `0xA0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMERSINTSTAT` `RO 0x0`
`TIMERSEOI` `0xA4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMERSEOI` `RO 0x0`
`TIMERSRAWINTSTAT` `0xA8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMERSRAWINTSTAT` `RO 0x0`
`TIMERSCOMPVERSION` `0xAC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIMERSCOMPVERSION` `RO 0x3230392A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIMERSCOMPVERSION` `RO 0x3230392A`
`i_timer_sp_1_DW_apb_timers_addr_block`
`TIMER1LOADCOUNT` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIMER1LOADCOUNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIMER1LOADCOUNT` `RW 0x0`
`TIMER1CURRENTVAL` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIMER1CURRENTVAL` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIMER1CURRENTVAL` `RO 0x0`
`TIMER1CONTROLREG` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`TIMER_INTERRUPT_MASK` `RW 0x0`	`TIMER_MODE` `RW 0x0`	`TIMER_ENABLE` `RW 0x0`
`TIMER1EOI` `0xC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMER1EOI` `RO 0x0`
`TIMER1INTSTAT` `0x10` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMER1INTSTAT` `RO 0x0`
`TIMERSINTSTAT` `0xA0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMERSINTSTAT` `RO 0x0`
`TIMERSEOI` `0xA4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMERSEOI` `RO 0x0`
`TIMERSRAWINTSTAT` `0xA8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`TIMERSRAWINTSTAT` `RO 0x0`
`TIMERSCOMPVERSION` `0xAC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TIMERSCOMPVERSION` `RO 0x3230392A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TIMERSCOMPVERSION` `RO 0x3230392A`