TIMERSINTSTAT

         Name: Timers Interrupt Status Register
Size: 1-8 bits
Address Offset: 0xa0
Read/Write Access: Read

Module Instance	Base Address	Register Address
`i_timer_sp_0_DW_apb_timers_addr_block`	`0xFFC03000`	`0xFFC030A0`
`i_timer_sp_1_DW_apb_timers_addr_block`	`0xFFC03100`	`0xFFC031A0`

Size: 32

Offset: 0xA0

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`TIMERSINTSTAT` `RO 0x0`

TIMERSINTSTAT Fields

Bit

Name

Description

Access

Reset

TIMERSINTSTAT

Contains the interrupt status of all timers in the component. If a bit of
this register is 0, then the corresponding timer interrupt is not active
and the corresponding interrupt could be on either the timer_intr bus
or the timer_intr_n bus, depending on the interrupt polarity you have
chosen. Similarly, if a bit of this register is 1, then the corresponding
interrupt bit has been set in the relevant interrupt bus. In both cases,
the status reported is the status after the interrupt mask has been
applied. Reading from this register does not clear any active
interrupts:
0 = either timer_intr or timer_intr_n is not active after masking
1 = either timer_intr or timer_intr_n is active after masking.

Value	Description
0x0	Timer_intr(_n) is inactive
0x1	Timer_intr(_n) is active

RO

0x0