firewall_mpu_ddr Address Map

DDR Security Control Registers (SCR)
Module Instance Base Address End Address
soc_noc_fw_ddr_mpu_inst_0_ddr_scr 0xF8020200 0xF80203FF
Register Offset Width Access Reset Value Description
enable 0x0 32 RW 0x00000000 
Enable
enable_set 0x4 32 WO 0x00000000 
Sets Master Region Enable field when written with 1
enable_clear 0x8 32 WO 0x00000000 
Clears Master Region Enable field when written with 1
mpuregion0addr_base 0x10 32 RW 0x00000000 
Base definition for MPU Region 0
mpuregion0addr_baseext 0x14 32 RW 0x00000000 
base extended definition for MPU Region 0
mpuregion0addr_limit 0x18 32 RW 0x0000FFFF 
Limit definition for MPU Region 0
mpuregion0addr_limitext 0x1C 32 RW 0x00000000 
limit extended definition for MPU Region 0
mpuregion1addr_base 0x20 32 RW 0x00000000 
Base definition for MPU Region 1
mpuregion1addr_baseext 0x24 32 RW 0x00000000 
base extended definition for MPU Region 1
mpuregion1addr_limit 0x28 32 RW 0x0000FFFF 
Limit definition for MPU Region 1
mpuregion1addr_limitext 0x2C 32 RW 0x00000000 
limit extended definition for MPU Region 1
mpuregion2addr_base 0x30 32 RW 0x00000000 
Base definition for MPU Region 2
mpuregion2addr_baseext 0x34 32 RW 0x00000000 
base extended definition for MPU Region 2
mpuregion2addr_limit 0x38 32 RW 0x0000FFFF 
Limit definition for MPU Region 2
mpuregion2addr_limitext 0x3C 32 RW 0x00000000 
limit extended definition for MPU Region 2
mpuregion3addr_base 0x40 32 RW 0x00000000 
Base definition for MPU Region 3
mpuregion3addr_baseext 0x44 32 RW 0x00000000 
base extended definition for MPU Region 3
mpuregion3addr_limit 0x48 32 RW 0x0000FFFF 
Limit definition for MPU Region 3
mpuregion3addr_limitext 0x4C 32 RW 0x00000000 
limit extended definition for MPU Region 3
mpuregion4addr_base 0x50 32 RW 0x00000000 
Base definition for MPU Region 4
mpuregion4addr_baseext 0x54 32 RW 0x00000000 
base extended definition for MPU Region 4
mpuregion4addr_limit 0x58 32 RW 0x0000FFFF 
Limit definition for MPU Region 4
mpuregion4addr_limitext 0x5C 32 RW 0x00000000 
limit extended definition for MPU Region 4
mpuregion5addr_base 0x60 32 RW 0x00000000 
Base definition for MPU Region 5
mpuregion5addr_baseext 0x64 32 RW 0x00000000 
base extended definition for MPU Region 5
mpuregion5addr_limit 0x68 32 RW 0x0000FFFF 
Limit definition for MPU Region 5
mpuregion5addr_limitext 0x6C 32 RW 0x00000000 
limit extended definition for MPU Region 5
mpuregion6addr_base 0x70 32 RW 0x00000000 
Base definition for MPU Region 6
mpuregion6addr_baseext 0x74 32 RW 0x00000000 
base extended definition for MPU Region 6
mpuregion6addr_limit 0x78 32 RW 0x0000FFFF 
Limit definition for MPU Region 6
mpuregion6addr_limitext 0x7C 32 RW 0x00000000 
limit extended definition for MPU Region 6
mpuregion7addr_base 0x80 32 RW 0x00000000 
Base definition for MPU Region 7
mpuregion7addr_baseext 0x84 32 RW 0x00000000 
base extended definition for MPU Region 7
mpuregion7addr_limit 0x88 32 RW 0x0000FFFF 
Limit definition for MPU Region 7
mpuregion7addr_limitext 0x8C 32 RW 0x00000000 
limit extended definition for MPU Region 7
nonmpuregion0addr_base 0x90 32 RW 0x00000000 
Base definition for non MPU Region 0
nonmpuregion0addr_baseext 0x94 32 RW 0x00000000 
base extended definition for non MPU Region 0
nonmpuregion0addr_limit 0x98 32 RW 0x0000FFFF 
Limit definition for non MPU Region 0
nonmpuregion0addr_limitext 0x9C 32 RW 0x00000000 
limit extended definition for non MPU Region 0
nonmpuregion1addr_base 0xA0 32 RW 0x00000000 
Base definition for non MPU Region 1
nonmpuregion1addr_baseext 0xA4 32 RW 0x00000000 
base extended definition for non MPU Region 1
nonmpuregion1addr_limit 0xA8 32 RW 0x0000FFFF 
Limit definition for non MPU Region 1
nonmpuregion1addr_limitext 0xAC 32 RW 0x00000000 
limit extended definition for non MPU Region 1
nonmpuregion2addr_base 0xB0 32 RW 0x00000000 
Base definition for non MPU Region 2
nonmpuregion2addr_baseext 0xB4 32 RW 0x00000000 
base extended definition for non MPU Region 2
nonmpuregion2addr_limit 0xB8 32 RW 0x0000FFFF 
Limit definition for non MPU Region 2
nonmpuregion2addr_limitext 0xBC 32 RW 0x00000000 
limit extended definition for non MPU Region 2
nonmpuregion3addr_base 0xC0 32 RW 0x00000000 
Base definition for non MPU Region 3
nonmpuregion3addr_baseext 0xC4 32 RW 0x00000000 
base extended definition for non MPU Region 3
nonmpuregion3addr_limit 0xC8 32 RW 0x0000FFFF 
Limit definition for non MPU Region 3
nonmpuregion3addr_limitext 0xCC 32 RW 0x00000000 
limit extended definition for non MPU Region 3
nonmpuregion4addr_base 0xD0 32 RW 0x00000000 
Base definition for non MPU Region 4
nonmpuregion4addr_baseext 0xD4 32 RW 0x00000000 
base extended definition for non MPU Region 4
nonmpuregion4addr_limit 0xD8 32 RW 0x0000FFFF 
Limit definition for non MPU Region 4
nonmpuregion4addr_limitext 0xDC 32 RW 0x00000000 
limit extended definition for non MPU Region 4
nonmpuregion5addr_base 0xE0 32 RW 0x00000000 
Base definition for non MPU Region 5
nonmpuregion5addr_baseext 0xE4 32 RW 0x00000000 
base extended definition for non MPU Region 5
nonmpuregion5addr_limit 0xE8 32 RW 0x0000FFFF 
Limit definition for non MPU Region 5
nonmpuregion5addr_limitext 0xEC 32 RW 0x00000000 
limit extended definition for non MPU Region 5
nonmpuregion6addr_base 0xF0 32 RW 0x00000000 
Base definition for non MPU Region 6
nonmpuregion6addr_baseext 0xF4 32 RW 0x00000000 
base extended definition for non MPU Region 6
nonmpuregion6addr_limit 0xF8 32 RW 0x0000FFFF 
Limit definition for non MPU Region 6
nonmpuregion6addr_limitext 0xFC 32 RW 0x00000000 
limit extended definition for non MPU Region 6
nonmpuregion7addr_base 0x100 32 RW 0x00000000 
Base definition for non MPU Region 7
nonmpuregion7addr_baseext 0x104 32 RW 0x00000000 
base extended definition for non MPU Region 7
nonmpuregion7addr_limit 0x108 32 RW 0x0000FFFF 
Limit definition for non MPU Region 7
nonmpuregion7addr_limitext 0x10C 32 RW 0x00000000 
limit extended definition for non MPU Region 7