enable_clear 

         Clears Master Region Enable field when written with 1
Module Instance Base Address Register Address
soc_noc_fw_ddr_mpu_inst_0_ddr_scr 0xF8020200 0xF8020208

Size: 32

Offset: 0x8

Access: WO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nonmpuregion7enable

WO 0x0

nonmpuregion6enable

WO 0x0

nonmpuregion5enable

WO 0x0

nonmpuregion4enable

WO 0x0

nonmpuregion3enable

WO 0x0

nonmpuregion2enable

WO 0x0

nonmpuregion1enable

WO 0x0

nonmpuregion0enable

WO 0x0

mpuregion7enable

WO 0x0

mpuregion6enable

WO 0x0

mpuregion5enable

WO 0x0

mpuregion4enable

WO 0x0

mpuregion3enable

WO 0x0

mpuregion2enable

WO 0x0

mpuregion1enable

WO 0x0

mpuregion0enable

WO 0x0

enable_clear Fields

Bit Name Description Access Reset
15 nonmpuregion7enable 
non MPU Region 7 Enable Clear.
Writing zero has no effect
Writing one will clear the region7enable bit to zero
 WO 0x0
14 nonmpuregion6enable 
non MPU Region 6 Enable Clear.
Writing zero has no effect
Writing one will clear the region7enable bit to zero
 WO 0x0
13 nonmpuregion5enable 
non MPU Region 5 Enable Clear.
Writing zero has no effect
Writing one will clear the region7enable bit to zero
 WO 0x0
12 nonmpuregion4enable 
non MPU Region 4 Enable Clear.
Writing zero has no effect
Writing one will clear the region7enable bit to zero
 WO 0x0
11 nonmpuregion3enable 
non MPU Region 3 Enable Clear.
Writing zero has no effect
Writing one will clear the region7enable bit to zero
 WO 0x0
10 nonmpuregion2enable 
non MPU Region 2 Enable Clear.
Writing zero has no effect
Writing one will clear the region7enable bit to zero
 WO 0x0
9 nonmpuregion1enable 
non MPU Region 1 Enable Clear.
Writing zero has no effect
Writing one will clear the region7enable bit to zero
 WO 0x0
8 nonmpuregion0enable 
non MPU Region 0 Enable Clear.
Writing zero has no effect
Writing one will clear the region7enable bit to zero
 WO 0x0
7 mpuregion7enable 
MPU Region 7 Enable Clear.
Writing zero has no effect
Writing one will clear the region7enable bit to zero
 WO 0x0
6 mpuregion6enable 
MPU Region 6 Enable Clear.
Writing zero has no effect
Writing one will clear the region6enable bit to zero
 WO 0x0
5 mpuregion5enable 
MPU Region 5 Enable Clear.
Writing zero has no effect
Writing one will clear the region5enable bit to zero
 WO 0x0
4 mpuregion4enable 
MPU Region 4 Enable Clear.
Writing zero has no effect
Writing one will clear the region4enable bit to zero
 WO 0x0
3 mpuregion3enable 
MPU Region 3 Enable Clear.
Writing zero has no effect
Writing one will clear the region3enable bit to zero
 WO 0x0
2 mpuregion2enable 
MPU Region 2 Enable Clear.
Writing zero has no effect
Writing one will clear the region2enable bit to zero
 WO 0x0
1 mpuregion1enable 
MPU Region 1 Enable Clear.
Writing zero has no effect
Writing one will clear the region1enable bit to zero
 WO 0x0
0 mpuregion0enable 
MPU Region 0 Enable Clear.
Writing zero has no effect
Writing one will clear the region0enable bit to zero
 WO 0x0