Apollo Lake

The Intel Atom® processor E3900 series, Intel® Celeron® processor N3350, and Intel® Pentium® processor N4200 platform, formerly Apollo Lake, empowers real-time computing in digital surveillance, new in-vehicle experiences, advancements in industrial and office automation, new solutions for retail and medical, and more. These processors are based on the Goldmont architecture, utilizing Intel’s industry-leading 14 nm process technology.

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Development User Guides(5)

On-Demand Training(8)

Product Discontinuance Notices (PDN)(1)

Release Notes(1)

Solution Briefs(1)

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Title

ID

Date

Version

Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID: 683152

Date:01/23/25

Version:

Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID: 683456

Date:01/23/25

Version:

Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID: 683349

Date:01/23/25

Version:

Intel® High Level Synthesis Compiler Pro Edition: Getting Started Guide

ID: 683680

Date:01/23/25

Version:

Intel® High Level Synthesis Compiler Pro Edition: Version 24.1 Release Notes

ID: 683682

Date:01/23/25

Version:

Image for: PDN2404 Altera is Discontinuing Selected HLS Compiler Software Ordering Codes

PDN2404 Altera is Discontinuing Selected HLS Compiler Software Ordering Codes

ID: 820203

Date:04/08/24

Version:1.0.0

HLS Loop Optimizations (Part 3 of 7)

ID: 653084

Date:09/08/21

Version:

HLS Interfaces (Part 2 of 7)

ID: 653070

Date:09/08/21

Version:

Introduction to High-Level Synthesis (Part 1 of 7)

ID: 652983

Date:09/08/21

Version:

HLS Data Types (Part 4 of 7)

ID: 652941

Date:09/08/21

Version:

HLS Performance Optimization (Part 6 of 7)

ID: 652867

Date:09/08/21

Version:

HLS Local Memory Optimizations (Part 5 of 7)

ID: 652862

Date:09/08/21

Version:

HLS Coding Optimizations for Intel® Stratix® 10 Devices

ID: 652821

Date:09/08/21

Version:

HLS Optimization Example: Matrix Decomposition (Part 7 of 7)

ID: 652819

Date:09/08/21

Version:

Image for: Low-Latency Data Mover Framework from Algo-Logic* with Intel® FPGA PAC D5005 Solution Brief

Low-Latency Data Mover Framework from Algo-Logic* with Intel® FPGA PAC D5005 Solution Brief

ID: 649763

Date:12/03/20

Version:

Image for: Intel® High Level Synthesis Compiler Condensed Quick Reference

Intel® High Level Synthesis Compiler Condensed Quick Reference

ID: 653699

Date:05/01/19

Version: