Intel® Stratix® 10 DX FPGA
Intel® Stratix® 10 DX FPGA and SoC FPGA devices enable next generation high bandwidth applications ranging from cache-coherent accelerators, custom servers for Cloud Service Providers (CSPs), and higher performance SmartNICs. They are the first FPGA devices to support Intel® Ultra Path Interconnect (Intel® UPI) for direct coherent connection to future select Intel® Xeon® Scalable processors. They also include PCIe* 4.0 x16 interface for connection to 3rd Gen Intel® Xeon® Scalable Platform and support for select Intel® Optane™ DC persistent memory products.
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Intel® Stratix® 10 DX FPGA
Features and Benefits
Up to 2x More PCIe* Bandwidth Enabled Through PCIe 4.01
Coherent connection to future select Intel® Xeon® Scalable processors and faster connectivity through PCIe hard and soft intellectual property (IP) blocks in supports up to 4.0 x16 at 16GT/s per lane with port bifurcation: 2x8 endpoint or 4x4 rootport modes.
Up to 37% Lower Latency on Coherent Connection Through UPI2 3
Intel® Ultra Path Interconnect (Intel® UPI) hard IP with up to 20 lanes at 11.2GT/s for direct cache coherent connection to future select Intel® Xeon® Scalable processors.
Support for HBM2, SoC, and Select Intel® Optane™ Persistent Memory
Intel® Stratix® 10 DX device variants come with up to 8GB of integrated High Bandwidth Memory 2 (HBM2) DRAM at 512GBps bandwidth or a 64 bit quad-core Arm* Cortex-A53 Hard Processor Subsystem and support for select Intel® Optane™ DC persistent memory.
Enabling the Future of Networking
Intel® Stratix® 10 DX devices deliver dual-mode modulation, 57.8 Gbps PAM4, and 28.9 Gbps NRZ enabling early adoption of next generation data infrastructure and backward-compatibility with existing infrastructure in network functions virtualization, cloud computing, and 5G wireless industries.
Watch the Introduction Video to Intel Stratix 10 DX FPGA
Introducing Intel® Stratix® 10 DX FPGA for your high bandwidth and evolving data center requirements. It is the first FPGA to support Intel® Ultra Path Interconnect (UPI), PCIe 4.0 x16 and select Intel® Optane™ DC persistent memory DIMMs. Watch this video to learn more!
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Product and Performance Information
Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Intel® Quartus® Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to Intel® Hyperflex™ FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users will achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.