Serial Lite IV Intel® FPGA IP Core

The Serial Lite IV Intel® FPGA Intellectual Property (IP) core is suitable for high-bandwidth data communication for chip-to-chip, board-to-board, and backplane applications.

Read the Serial Lite IV Intel® FPGA IP user guide ›

Read the GTS Serial Lite IV Intel® FPGA IP User Guide ›

Read the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide ›

Serial Lite IV Intel® FPGA IP Core

Serial Lite IV IP core incorporates a media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) block. The IP supports data transfer up to 58 Gbps per lane with a maximum of 12 PAM4 lanes of the Intel® Agilex™ 7 F-tile General-Purpose Transceivers (FGT) and up to 116 Gbps with a maximum of 4 PAM4 lanes of the Intel® Agilex™ 7 F-tile High-Speed Transceivers (FHT) in a single link or 28 Gbps per lane with a maximum of 16 non-return-to-zero (NRZ) lanes of FGT and 58 Gbps per lane with a maximum of 4 NRZ lanes of FHT. This protocol offers high bandwidth, low overhead frames, and low I/O count supporting high scalability in both numbers of lanes and speed. The IP is easily reconfigurable with support of a wide range of data rates with Ethernet PCS mode of the E-Tile transceiver and the F-Tile transceiver with our latest GTS transceivers for the Agilex™ 5 devices.

This IP supports two transmission modes:

  • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
  • Full mode—This is the packet mode of data transfer. A burst and sync cycle is sent at the start and at the end of a packet as delimiters.

Features

Feature Description
Data Transfer
  • Supports up to 116 Gbps per lane with a maximum of 4 PAM4 lanes of FHT in a single link
  • Supports up to 58 Gbps per lane with a maximum of 4 NRZ lanes of FHT in a single link.
  • Supports up to 58 Gbps per lane with a maximum of 12 PAM4 lanes of FGT in a single link.
  • Supports up to 28 Gbps per lane with a maximum of 16 NRZ lanes of FGT in a single link.
  • Supports continuous streaming (Basic) or packet (Full) modes.
  • Supports low overhead frame packets.
  • Supports byte granularity transfer for every burst size.
  • Supports user-initiated or automatic lane alignment.
  • Supports programmable alignment period.
PCS
  • Uses hard IP logic that interfaces seamlessly to Intel® Agilex™ 7 and Intel® Stratix® 10 device E-Tile transceivers for soft logic resource reduction.
  • Supports PAM4 modulation mode for 100GBASE-KP4 specification. RS-FEC is always enabled in this modulation mode.
  • Supports NRZ modulation mode with (optional) KR-FEC error detection and correction.
  • Supports 64b/66b encoding decoding.
Error Detection and Handling
  • Supports cyclic redundancy check (CRC) error checking on transmit (TX) and receive (RX) datapaths.
  • Supports RX link error checking.
  • Supports RX PCS error detection.
Interfaces
  • Supports only full duplex packet transfer with independent links.
  • Uses point-to-point interconnect to multiple FPGAs with low transfer latency.
  • Supports user-defined commands.
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IP Status

IP Ordering Codes Ordering Status
Serial Lite IV Intel® FPGA IP IP-SLITE4 Production
F-Tile Serial Lite IV Intel FPGA IP IP-SLITE4F Production

GTS Serial Lite IV Intel FPGA IP

IP-SLITE4F

 Preliminary
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