MIPI D-PHY IP
Mobile Industry Processor Interface (MIPI) D-PHY is supported exclusively on Agilex™ 5 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.
MIPI D-PHY
MIPI D-PHY feature supports high-speed (HS) and low-power (LP) modes and allows direct interface with the D-PHY compliance component without external components.
Supports low-power and high-speed signaling up to 3.5 Gbps* per lane.
Supports AXI-Lite interface for seamless video transmission and reception.
Enables unidirectional multi-lane configurations 1, 2, 4, or 8 lanes.
MIPI CSI-2
- Latency Reduction and Transport Efficiency (LRTE) for image-sensor aggregation without adding to the overall system cost.
- Differential Pulse Code Modulation (DPCM) compression for seamless compression of HD images for mission critical applications.
- Reducing the number of wires in a system like IoT by using the Unified Serial Link (USL).
- Scrambling reduces Power Spectral Density (PSD) emissions for longer channels.
*Only in Agilex™ 5 FPGA E-Series Group A and D-Series devices.
- 4K and 8K Image and Video Streaming.
- Automotive – ADAS, In-Vehicle Infotainment, Electrification & Networking.
- Sensor imaging and connectivity on UAV and Robotic Platforms.
- Virtual Reality Headsets, Camera-enabled robots and drones.
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