JESD204C Altera® FPGA IP

The JESD204C Altera® FPGA IP is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to FPGA devices.

Read the JESD204C Altera® FPGA IP user guide ›

Read the JESD204C Agilex™ 7 F-Tile FPGA IP user guide ›

Read the GTS JESD204C Altera® FPGA IP User Guide ›

Read the E-Tile JESD204C Altera® FPGA IP User Guide ›

Read the F-Tile JESD204C Altera® FPGA IP User Guide ›

JESD204C Altera® FPGA IP

The JESD204C Altera® FPGA IP incorporates:

  • Media access control (MAC)—data link layer (DLL) and transport layer (TL) blocks that control the link states.
  • Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.

Features

The JESD204C Altera® FPGA IP core delivers the following key features:

  • Data rate of up to 32.44032 Gbps for Agilex™ 7 F-tile devices and 28.9 Gbps for Agilex™ 7 E-tile devices and Stratix® 10 E-tile devices, and 17.16 Gbps for Agilex™ 5 E-Series devices.
  • Single or multiple lanes (up to 16 lanes per link)
  • Local extended multiblock clock (LEMC) counter based on E=1 to 256
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multidevice synchronization
  • MAC and PHY partitioning
  • Deterministic latency support
  • 64/66 encoding
  • Scrambling/descrambling
  • Avalon® streaming interface for transmit and receive datapaths
  • Avalon® memory-mapped interface for control/status registers (CSR)
  • Dynamic generation of simulation test bench
  • Bonded and non-bonded TX PMA mode
  • Optional support for ECC M20K DCFIFO
  • Options for sync header configurations
  • CRC-12
  • Stand-alone command channels

IP Status

 

Ordering Status

Production

Ordering Codes

Altera® FPGA IP JESD204 SUITE

IPS-JESD204 (contains JESD204B, JESD204B-FTILE, JESD204C, JESD204C-FTILE)
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