Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core

The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate both the hard standard physical coding sublayer (PCS) and the higher performance hard 10G PCS, and hard physical medium attachment (PMA) for a single Backplane Ethernet channel. It implements the functionality described in the IEEE 802.3ap-2007 standard. Because each instance of the 10GBASE-KR PHY IP core supports a single channel, you can create multichannel designs by instantiating more than one instance of the core.

Read the Intel® Stratix® 10 10GBASE-KR PHY IP Core user guide ›

Read the Intel® Arria® 10 Transceiver PHY user guide ›

Read the Stratix® V device handbook ›

Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core

Features

  • Integrated 1000BASE-KX / 10GBASE-KR (1G/10Gb) backplane Ethernet PCS and PMA
  • Direct internal interface with Intel® FPGA 1G/10GbE media access controller (MAC) for a complete single-chip solution
  • 10GBASE-KR auto negotiation for negotiating between 1000BASE-KX (1 Gbps Ethernet or 1GbE) and 10GBASE-KR (10 Gbps Ethernet or 10GbE) PHY types per clause 73 of the IEEE 802.3ap-2007 standard
  • Link training to automatically configure the remote link partner transmitter physical media driver (PMD) for the lowest bit error rate (BER) per clause 72 of IEEE 802.3ap-2007 standard
  • Forward error correction (FEC) to minimize retransmission in accordance to IEEE 802.3 and 802.3ba clause 74
  • Internal programmable algorithm for the receiver adaptation process per IEEE 8023.ap clause 72.6.10.2.3 for ease of use
  • Flexible IP user controls for performance optimization in various system configurations and channels
  • Receiver-link fault status detection
  • Local serial loop-back from transmitter to receiver at the serial transceiver for self test
  • High-performance internal system interfaces
  • GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE MAC, 8 bits at 125 MHz and 72 bits at 156.25 MHz respectively for data transfer
  • Intel® FPGA Avalon® Memory-Mapped (PDF) (Avalon-MM) 32 bit interface for agent management

IP Status

 

Ordering Status

Production

Ordering Codes

Intel® Stratix® 10 10GBASE-KR PHY IP Core

IP-10GBASEKRPHY

Intel® Arria® 10 Transceiver PHY

IP-10GMRPHY
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