Arria® V FPGA and SoC FPGA

The Arria® V FPGA family offers the highest bandwidth and delivers the lowest total power for midrange applications, such as remote radio units, 10G/40G line cards, and broadcast studio equipment. There are five targeted variants, including SoC variants with a dual-core ARM* Cortex*-A9 hard processor system (HPS) to best meet your performance, power, and integration needs.

Arria® V FPGA and SoC FPGA

Family Variations

Feature	Arria® V GZ FPGA	Arria® V GT FPGA	Arria® V GX FPGA	Arria® V ST SoC	Arria® V SX SoC
ALMs (K)	170	190	190	174	174
Variable-Precision DSP	1,139	1,156	1,156	1,068	1,068
M20K Blocks	1,700	-	-	-	-
M10K Blocks	-	2,414	2,414	2,282	2,282
DDR3 Memory Interface Speed	800 MHz	667 MHz	667 MHz	667 MHz	667 MHz
Hard Memory Controllers	-	4	4	4	4
Transceivers (Gbps)	12.5 Gbps	10.3125	6.5536	10.3125	6.5536
*PCI Express® (PCIe) Gen3/2/1 hardened IP block**	1	-	-	-	-
*PCIe Gen2/1 hardened IP blocks(s)**	-	2	2	2	2
Design Security	x	x	x	x	x
Single Event Upset (SEU) Mitigation	x	x	x	x	x

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Arria® V Architecture

Flexible Transceivers

Whether you need a few channels of transceivers, or up to 36, Arria® V FPGAs provide transceiver solutions to meet your performance and power requirements to deliver exactly what you need to succeed. Flexible clocking, superior signal integrity (SI), the lowest power transceivers, and the highest quantity of transceivers are only a handful of the ways the Arria® V FPGAs have been designed for power-sensitive, high-bandwidth applications.

Each Arria® V FPGA transceiver consists of the Physical Media Attachment, Physical Coding Sublayer, and hardened IP blocks with added clocking flexibilities and more independent channels. Every channel has a full PMA and PCS along with a dedicated independent receive analog PLL CDR. To make it easier for designers to meet transceiver speeds up to 12.5 Gbps, drive up to 40" of backplane, and implement PCIe* Gen3, Arria® V GZ contains a number of additional features.

*Note: Arria® V GX, and GT do not have Adaptive LinearEQ, EyeQ, PCIe* Gen3 and select hardened IP that Arria® V GZ has.

Optimized for Low Power and Low System Cost

A single 10.3125-Gbps channel will consume < 165 mW of power.
A single 12.5-Gbps channel will consume < 200 mW of power.

Features	Arria® V GZ	Arria® V GT	Arria® V GX
Maximum number of transceivers	36	36	36
12.5 Gbps backplane capable transceivers	x	-	-
10.3125 Gbps transceivers for SFF-8431 applications	x	x	-
6.375 backplane capable transceivers	x	x	x
Continuous-time linear equalization - Receiver 4-stage linear equalization	x	-	-
Decision feedback equalization - Receiver 5-tap digital equalizer	x	-	-
Adaptive equalization - Automatically adjust equalization	x	-	-
Linear equalizer	-	x	x
Transmit equalization pre-emphasis (4-Tap)	x	-	-
Transmit equalization pre-emphasis (3-Tap)	-	x	x
Ring oscillator transmit PLLs	x	x	x
LC oscillator PLLs	x	-	-
On-die instrumentation (EyeQ data-eye monitor)	x	-	-

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Variable-Precision DSP Block

To meet demands for higher precision signal processing, we have developed the industry's first variable-precision digital signal processing (DSP) block. This integrated block, part of the Stratix® V, Arria® V, and Cyclone® V FPGA 28-nm DSP Portfolio, allows each block to be configured at compile time into an 18-bit mode or in a high-precision mode.

With the variable-precision DSP block, the Arria® V and Cyclone® V FPGAs support, on a block-by-block basis, various precisions ranging from 9-bit x 9-bit up to single-precision floating point (mantissa multiplication) within a single DSP block. This frees you from FPGA architecture restrictions, allowing you to use the optimum precision at each stage of the DSP datapath. You'll also benefit from increased system performance, reduced power consumption, and reduced architectural constraints.

The variable-precision DSP block in Arria® V and Cyclone® V FPGAs are optimized to provide the following enhancements:

108 inputs, 74 outputs.
18x19 multiply mode, allowing the pre-adder to use two 18-bit inputs.
Optional second accumulator (feedback register) for complex serial filtering.
Dual 18x19 independent multipliers.
No restriction on use of hard pre-adder and external coefficients in 18-bit mode.

Arria® V and Cyclone® V FPGA Multiplier Precision Range in Single- and Multiple-Block Modes

Arria® V and Cyclone® V FPGA Multipliers in Single-Block Mode

Number of Multipliers	Multiplier Precision
Three independent multipliers	9x9
Two multipliers in sum mode	18x19
Two independent multipliers	18x19
One independent asymmetric multiplier	18x36 (requires additional logic outside the DSP block)
One independent high-precision multiplier	27x27

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Arria® V and Cyclone® V FPGA Multipliers in Multiple-Block Mode

Type of Multipliers	Number of Blocks Required
One independent 36x36 multiplier	2 (requires additional logic outside the DSP block)
One independent 54x54 multiplier	4 (requires additional logic outside the DSP block)
One 18x18 complex multiplier	2
One 18x25 complex multiplier	4 (requires additional logic outside the DSP block)
One 18x36 complex multiplier	4 (requires additional logic outside the DSP block)
One 27x27 complex multiplier	4

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Cascade Bus

All modes feature a 64-bit accumulator and each variable-precision DSP block comes with a 64-bit cascade bus that allows implementation of even higher precision signal processing by cascading multiple blocks using a dedicated bus.

The variable-precision DSP architecture maintains backward compatibility. It can efficiently support existing 18-bit DSP applications, such as high-definition video processing, digital up or down conversion, and multi-rate filtering.

SoC FPGA Hard Processor System

Intel® SoC FPGAs integrate an ARM*-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The Arria® V SoC FPGAs reduce system power, system cost, and board size while increasing system performance by integrating discrete processor, FPGA, and digital signal processing (DSP) functions into a single, user customizable ARM*-based system on a chip (SoC). SoCs provide the ultimate combination of hardened intellectual property (IP) for performance and power savings, with the flexibility of programmable logic.

HPS Features

Each processor core includes:
32 KB of L1 instruction cache, 32 KB of L1 data cache
Single- and double-precision floating-point unit and NEONTM media engine
CoreSightTM debug and trace technology
512 KB of shared L2 cache with error correction code (ECC) support
64 KB of scratch RAM with ECC support
Multiport SDRAM controller with support for DDR2, DDR3, and LPDDR2 as well as optional ECC support
8-channel direct memory access (DMA) controller
QSPI flash controller
NAND flash controller with DMA
SD/SDIO/MMC controller with DMA
2x 10/100/1000 Ethernet media access control (MAC) with DMA
2x USB On-The-Go (OTG) controller with DMA
4x I2C controller
2x UART
2x serial peripheral interface (SPI) master peripherals, 2x SPI slave peripherals
Up to 134 general-purpose I/O (GPIO)
7x general-purpose timers
4x watchdog timers

High-Bandwidth HPS-to-FPGA Interconnect Backbone

Although the HPS and the FPGA can operate independently, they are tightly coupled via a high-bandwidth system interconnect built from high-performance ARM* AMBA* AXI bus bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-HPS interconnect. Similarly, HPS bus masters have access to bus slaves in the FPGA fabric via the HPS-to-FPGA bridge. Both bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. An additional 32-bit light-weight HPS-to-FPGA bridge provides low latency interface between the HPS and peripherals in the FPGA fabric. Up to six FPGA masters can share the HPS SDRAM controller with the processor. Additionally, the processor can be used to configure the FPGA fabric under program control via a dedicated 32-bit configuration port.

HPS-to-FPGA: configurable 32-, 64-, or 128-bit AMBA AXI interface optimized for high bandwidth
FPGA-to-HPS: configurable 32-, 64-, or 128-bit AMBA AXI interface optimized for high bandwidth
Lightweight HPS-to-FPGA: 32-bit AMBA AXI interface optimized for low latency
FPGA-to-HPS SDRAM controller: configurable multi-port interfaces with 6 command ports, 4x 64-bit read data ports and 4x 64-bit write data ports
~32-bit FPGA configuration manager

The 28 nm Arria® V FPGA family offers the lowest power, highest bandwidth FPGAs for mid-range applications, such as remote radio units, 10G/40G line cards, and in-studio mixers. A comprehensive offering of five device variants allows designers to optimally choose a solution that meets their price, performance, and power requirements. See the tables below for an overview of the Arria® V FPGA and SoC family and package choices.

Temperature Support

Device	Package	Speed Grade
Arria® V GZ	F780, F1152, F1517	C3, C4, I3L, I4
Arria® V SX/GX/ST/GT	F672, F896, F1152, F1517	C4, C5, C6, I3, I5

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