Intel® eASIC™ N5X Devices
Today’s emerging innovations in 5G wireless, Cloud and storage, AI, and edge applications require a broad range of new equipment, and one size no longer fits all. Intel® eASIC™ N5X devices offer an innovative solution to custom logic that provides up to 50% lower core power1 with lower unit-cost2 compared to FPGAs while providing faster time to market and lower non-recurring engineering costs when compared to cell based ASICs.3 4
Only Intel enables the complete custom logic continuum of FPGAs, structured ASICs, and ASICs to build equipment tailored to unique challenges of time to market (TTM), cost, power, volume, performance, and flexibility requirements.
Intel® eASIC™ N5X Devices
Intel® eASIC™ N5X Device Overview Tables
| N5X007 | N5X015 | N5X024 | N5X047 | N5X080 | |
|---|---|---|---|---|---|
| eCells (M) / Logic Elements (M) | 0.70 | 1.47 | 2.38 | 4.65 | 8.77 |
| Equivalent ASIC gates (M) | 7 | 15 | 24 | 47 | 88 |
| M10K Memory | 1,752 | 3,684 | 6,004 | 11,780 | 22,268 |
| M10K Memory (Mbits) | 17.11 | 35.98 | 58.63 | 115.04 | 217.46 |
| 128b register file | 12,446 | 26,082 | 42,448 | 82,453 | 154,770 |
| 128b register file (Mbits) | 1.52 | 3.18 | 5.18 | 10.07 | 18.89 |
| Mega SRAM & Mega SRAM 2 (Mbits) | - | - | - | - | 136 |
| Secure device manager | Secure data manager AES-256/SHA-256 bitstream encryption/authentication, ECDSA 256/384 boot code authentication, anti-tamper protection, 3 independent user root keys. Vendor authenticated boot (VAB), Secured data object storage (SDOS), Time and priority based key revocation. |
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| Hard Processor System | Quad-core 64-bit Arm Cortex-A53 up to 1.5GHz, with 32 KB Instruction/Data cache, NEON coprocessor, 1 MB L2 cache, direct memory access (Direct Memory Access), system memory management unit, cache coherency unit, hard memory controllers for DDR4/LPDDR4/LPDDR4x, USB 2.0x2, 1G eMac* x3, UART x2, SPI (Serial Peripheral Interface) x4, I2C x5, general purpose timers x7, watchdog timer x4. |
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| SoC IO EMIF* / Pin Mux / Dedicated | 140 / 48 / 24 | 140 / 48 / 24 | 140 / 48 / 24 | 140 / 48 / 24 | - |
| Max GPIO | 416 | 560 | 682 | 682 | 1,136 |
| XCVR32 | 16 | 24 | 32 | 64 | 48 |
| XCVR56 | - | - | - | - | 8 |
| Hard PCIe Gen5 x8 | - | - | - | - | 6 |
| Hard 200GbE MAC | - | - | - | - | 2 |
Intel® eASIC™ N5X Example Package Options
Packages can be customized per application requirements to replace an FPGA or reduce PCB footprint for a given application.
| Body size (mm x mm) |
Package Name | N5X007 | N5X015 | N5X024 | N5X047 | N5X080 |
|---|---|---|---|---|---|---|
| 27x27 | FC676, FC1085 | Yes | - | - | - | - |
| 29x29 | FC780, FC1221 | Yes | Yes | - | - | - |
| 31x31 | FC896 | Yes | Yes | Yes | - | - |
| 35x35 | FC1152 | Yes | Yes | Yes | - | - |
| 40x40 | FC1517 | - | Yes | Yes | Yes | Yes |
| 42.5x42.5 | FC1760 | - | - | Yes | Yes | Yes |
| 45x45 | FC1932 | - | - | - | - | Yes |
| 47.5x47.5 | FC2205 | - | - | - | - | Yes |
| 50x50 | FC2397 | - | - | - | - | Yes |
| 52.5x52.5 | FC2601 | - | - | - | - | Yes |
Features
Balance Low Power and Performance
Intel’s innovative via configuration technology enables up to 50% lower core power1 or to increase performance in the same power envelope compared to FPGAs.5 Power consumption is further reduced by disconnecting power from unused device resources minimizing static power consumption.
Optimized TCO
Intel® eASIC™ N5X innovations reduce die size for a given logic and IO capacity and lowers unit cost compared to FPGAs.2 Intel eASIC N5X devices significantly reduce NRE4 and can be completed in ½ the development time of a cell-based ASIC on comparable process technology.3
FPGA Replacement & Custom Packages
Intel® eASIC™ package offerings provide options to closely match an FPGA package footprint to simplify migration and reduce transition cost. Further cost reduction can be achieved using small form factor packages minimizing PCB footprint.
Configurable eCells
Intel’s innovative eCell can be configured as logic, arithmetic or flip-flops. This enables the platform to be optimized on a design by design basis for a combination of high performance logic, DSP or highly pipelined designs.
Transceivers & IO
Intel® eASIC™ N5X transceivers are multi-protocol supporting a wide range of connectivity and networking protocols with continuous rates from 250MHz to 32.44 Gbps. Flexible eIO pins support 1.0V to 1.8V IO natively and 2.5V and 3.3V with in package level shifters. DDR4 interfaces are supported at rates up to 3200Mbps with integrated PLL/DLL between every two IO banks.
Intel FPGA Compatible Processor System and Security
Intel’s innovative quad-core Arm® 64-bit hard processor subsystem (HPS) and secure device manager (SDM)6 are ported from Intel® Agilex™ FPGAs meeting security requirements for 5G and military applications throughout the entire product lifecycle from manufacturing, to deployment, to decommissioning of equipment. These systems facilitate compatible migration from FPGAs to Intel® eASIC™ N5X devices.
Design Flow
Intel® eASIC™ eTools offer a framework for design conversion and validation using a combination of internally developed and industry standard third-party tools. This includes synthesis and simulation libraries, IP wrappers to implement eASIC functions, scripts for code validation and running third party synthesis and simulation tools. Intel® Quartus® software Platform Designer is used for the hard processor system configuration. DSP Builder for Intel® FPGAs can also output FPGA and eASIC ready RTL code.
Product and Performance Information
Up to 50% lower power at same performance compared to FPGA – Power estimation completed by Intel July 28, 2020. Power estimated using Intel® Quartus® Prime Design Software 20.3 for Intel® Agilex™ FPGAs and pre-silicon projections for N5X devices. FPGA device is Intel® Agilex™ FPGA AGF014 and Intel® eASIC™ N5X device is N5X047. Logic and memory clock rates used are 500MHz and toggle rates are 33% for logic and 50% for memory for both devices.
Lower unit cost compared to FPGA – Unit cost is based on equivalent logic, memory, I/O, and transceiver implemented in Intel® FPGAs and Intel® eASIC™ devices using the same package size. Your costs and results may vary.
½ development time compared to ASIC - Development time compared to cell-based ASIC on similar process node.
Lower NRE, and engineering resources - NRE and engineering costs lower compared to standard cell ASIC due to fewer mask layer customizations and fewer design steps using predefined base arrays in structured ASICs. Your costs and results may vary.
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.
No product or component can be absolutely secure.